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Data Processing on Modern Hardware

News

Feb 10, 2011. In case someone can't find the information in myStudies: tommorrow's exam is going to take place in HG F 5.

Dec 6, 2010. Results of the course evaluation are out. Here are the multiple-choice part and your hand-written comments. Thanks for participating in the evaluation!

Sep 24, 2010. There is great interest by students to participate in this course. Given the large number of current registrations, we had to change the examination mode to a written exam that is going to take place in the examination session (end of January/beginning of February).

Course Description

The roots of many productive database systems today date back thirty years or more. Prominent systems such as IBM's System R or the then-research prototype Ingres were first developed in the 1970s and were designed to address the hardware landscape of the time: disks or even tapes were the only medium to hold reasonable amounts of data; main memory could be considered as truly random access; and the major cost factor in database processing was I/O.

Since that time, computer architectures have changed significantly. RAM chips have become cheap enough to make in-memory processing feasible; caches and other architectural details lead to non-uniform memory access cost (an increasingly relevant performance factor); and the omnipresence of multi-core systems adds a whole new class of complexity to the problem.

In this course we look at how architectural changes affect database systems. Rather than suffering from the increasing latency gap for accesses to main memory, for instance, we can use available CPU caches to our advantage. A cache-aware design can improve the performance of a database operation by orders of magnitude. Likewise, modern CPU features (such as vector instructions) or specialized CPUs (like IBM's Cell processor or the nVidia CUDA architecture) can accelerate database tasks if the respective implementation has beed designed carefully.

We will complement this course with many hands-on exercises, where we verify some of the presented techniques on commodity hardware.

Lecture Slides

Description PDF PDF 2x2 last updated
Introduction PDF PDF 2x2 Sep 26, 2010
Cache Awareness PDF PDF 2x2 Oct 13, 2010
Instruction Execution PDF PDF 2x2 Oct 24, 2010
Vectorization PDF PDF 2x2 Nov 15, 2010
Multiple Cores PDF PDF 2x2 Nov 15, 2010
Graphics Processors (GPUs) PDF PDF 2x2 Dec 1, 2010
FPGAs PDF PDF 2x2 Dec 6, 2010

Exercises

Description   PDF   last updated   Resources   Solutions
Assignment1:  Probing your Cache   PDF   Oct 11, 2010   none   solution-01.tar.bz2
Assignment2:  Cache Awareness in Databases   PDF   Oct 25, 2010   store.tar.bz2   solution-02.tar.bz2
Assignment3:  Partitioned Hash Join   PDF   Nov 10, 2010   phj.tar.bz2   solution-03.tar.bz2
Assignment4:  Vectorized (de)compression   PDF   Nov 21, 2010   simd.tar.bz2   solution-04.tar.bz2
Assignment5:  Query Execution on GPGPUs   PDF   Dec 13, 2010   gpgpu-store.tar.bz2   solution-05.tar.bz2
Assignment6:  Regular Expressions in Hardware   PDF   Nov 28, 2010   regex-testbench.tar.bz2   solution-06.tar.bz2

Material

This course is mostly based on very recent research work that is not (yet) covered in textbooks. Throughout the course we will give references to research papers (mostly published at major database conferences like VLDB or SIGMOD) for background reading.

Another important source are going to be the lecture slides for this course, which we will post on this website as the semester progresses.

Course Evaluation

This course was evaluated on November 15, 2010. Here are the aggregated evaluation results:

Course Hours

Important Note: The room assignment for this course has changed. Lecture and exercises have been relocated to CAB G 61.

Lecture
Mon, 9−11h, room CAB G 61 ― Instructor: Jens Teubner
Exercises
Mon, 11−12h, room CAB G 61 ― Instructor: Louis Woods

Additional Information

This course will be taught in english and is listed as course number 263-3502-00 in the ETH course catalog. You'll get 4 credit points for this 2V + 1Ü course.

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