Master's and Bachelor's Theses
The Systems Group has a variety of projects available, as possible topics for a Masters Thesis, a Semester Projects, or as labs for bachelors or masters students.
Proposals
- protected page lock Deploying RoFL at Scale [BT] (PDF, 92 KB)
- protected page lock End-to-End System Designs for Privacy [MT/BT] (PDF, 95 KB)
- protected page lock Cryptographic Audits for Secure Machine Learning [MT] (PDF, 96 KB)
- protected page lock Scheme-Independent FHE Compiler for TensorFlow [MT] (PDF, 75 KB)
- protected page lock Deploying Secure Computation on Heterogeneous Hardware [MT] (PDF, 285 KB)
- protected page lock Extend an FPGA Collective Offload Engine [MT] (PDF, 269 KB)
- protected page lock Distributed Application with an FPGA Collective Offload Engine [Semester Project/MT] (PDF, 270 KB)
- protected page lock Code generation for heterogeneous architectures [BT] (PDF, 165 KB)
- protected page lock Data Serialization Offload for FPGA-Based Smart-NICs[MT] (PDF, 216 KB)
- protected page lock Differential Private Data and Query Set Generation for Benchmarking (PDF, 85 KB)
- protected page lock From Threats to Concrete Harms: A New Approach to Privacy Threat Modeling [MT] (PDF, 84 KB)
- protected page lock Answering subjective queries using vector search [Semester Project] (PDF, 183 KB)
- protected page lock Optimizing Compound AI Systems [MT/Semester Project] (PDF, 92 KB)
There are several thesis projects available within the Enzian and Sockeye projects:
- protected page lock USB Subsystem Support for an OS Course [Practical work] (PDF, 90 KB)
- protected page lock Inter-processor Interrupts in Heterogeneous Systems [MT/BT] (PDF, 93 KB)
- protected page lock A BMC orchestration layer in Rust over seL4 [MT/BT] (PDF, 98 KB)
- protected page lock Complete semantics of the ARMv8.1-A Memory Management Unit [MT] (PDF, 91 KB)
- protected page lock Firmware Management for a Heterogeneous Platform [BT/Practical work] (PDF, 98 KB)
- protected page lock Runtime Verification with TeSSLa on Enzian [MT] (PDF, 96 KB)
- protected page lock Integrating ECI and TileLink [MT/Practical work] (PDF, 65 KB)
- protected page lock Complete semantics of the ARMv8-R Memory Protection Unit [MT] (PDF, 93 KB)
- protected page lock Hybrid FPGA-Accelerator Encryption [BT/MT] and Compression (PDF, 89 KB)
- protected page lock Complete semantics of the RISC-V Memory Management Unit [MT] (PDF, 96 KB)
- protected page lock Specifying the interconnect of the AMD/Xilinx Ultrascale+ MPSoC [MT] (PDF, 93 KB)
- protected page lock Semantics of the Intel 64 and ia32 Memory Management Unit [MT] (PDF, 93 KB)
- protected page lock Hardware assisted page access tracking [BT/MT] (PDF, 94 KB)
Contact Timothy Roscoe () if you are interested in any of them.