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Friday February 24, 2017
Start: 24.02.2017 12:15

CAB E 72

Markus Pilman (Snowflake Computing)

Title: Snowflake - A Data Warehouse built for the Cloud

Abstract:

Snowflake Is a young Silicon Valley startup that implements a data warehouse service in the cloud. Snowflake achieves scalability and elasticity by separating compute and storage. Snowflake provides data warehouse as a service: a user can spin up warehouses of different sizes and run queries on shared data. In this talk I will demo the Snowflake service and give a broad overview of the features and the architecture. Furthermore I will give a more detailed overview of our internal metadata store and my current project in this area.

Monday February 27, 2017
Start: 27.02.2017 17:15

Markus Pilman: PhD Defense

Title: Tell: An Elastic Database System for Mixed Workloads

HG D 22

Thursday March 09, 2017
Start: 09.03.2017 19:00

Event

The LLVM Compiler and Code Generation Social is a meetup to discuss compilation and code generation topics, with a special focus on LLVMclangPolly, and related projects. If you are interested in generating code for a variety of architectures, (static) program analyses for real world C/C++/OpenCL/CUDA programs, building your own programming language, register allocation and instruction selection, software hardening techniques, have an idea for a great optimization, or want to target GPUs or FPGA, .... This event is for you!

Our primary focus are free discussions between interested people  (+ beer and food). This is a great opportunity to get and discuss project ideas or to just learn about what people at ETH and around Zurich are doing.

Tech Talk "LIBXSMM: Low-Level Just-in-Time (JIT) In-Memory Code Generation" by Hans Pabst

LIBXSMM is a library for small dense and small sparse matrix-matrix multiplications (SMM) as well as for deep learning primitives such as small convolutions (DNN) targeting Intel Architecture. The highly optimized code leverages an innovative Just-In-Time in-memory code generation, which is based on a machine model rather than blind auto-tuning. The talk will not only shed some light on LIBXSMM's code generation, but also highlight optimizations targeting Intel AVX-512 as well as general advantages of the JIT-code generation. Further, the SMM code is serviced by a code registry, which can quickly dispatch generated code automatically.

Bio:

Hans Pabst is an application engineer mainly enabling open source scientific applications to take advantage of current and future hardware. Hans is working in Intel's High Performance and Throughput Computing (HPC) team focusing on scientific computing and parallel algorithms research, code optimizations, and hardware-software co-design.

 

Slides: grosser.es/presentations/2017-03-09--Hans-Pabst--libxsmm.pdf

Registration

Please register to help us plan attendence.

Who

  • Anybody interested 
  • ETH students and staff
  • LLVM developers and enthusiasts external to ETH

When

09.03.2017, 19:00

We aim to arrange a meetup the second Thursday of a months

Where

ETH Zurich, CAB, E72

Floorplan

The building closes at 19:00. If you are late, you need to call us to be let in. (We send out the number before the meeting).

What is LLVM?

LLVM is an open source project that provides a collection of modular compiler and toolchain technologies. It is centered around a modern SSA-based compiler around which an entire ecosystem of compiler technology was developed. Most well know is the clang C++ compiler, which is e.g. used to deploy iOS. Beyond this a diverse set of projects is developed under the umbrella of LLVM. These include code generators and assemblers for various interesting architectures, a jit compiler, a debugger, run-time libraries (C++ Standard Library, OpenMP, Opencl library), program sanity checkers, and many more. LLVM has itself grown out of a research project more than 10 years ago and is the base of many exciting research projects today:

https://scholar.google.ch/scholar?cites=7792455789532680075&as_sdt=2005&sciodt=0,5&hl=de

Contact

Tobias Grosser

 

Monday March 13, 2017
Start: 13.03.2017 15:30

CAB E 72

Speaker: Eyal Rozenberg (CWI Amsterdam)

Title: What are we missing for making CPUs obsolete for analytic DB query processing? (a GPU perspective)

Abstract:

The past several years have seen several initial efforts to speed up analytic DB query processing using discrete GPUs [1]. But DBMSes are complex software systems, which have seen decades of spirited evolution and optimization on CPUs - and GPU proponents have found it very challenging to catch up. Thus, only last year was a system presented [2] which suprasses MonetDB-level performance on TPC-H queries - and even that one wasn't released to the public. Still, there is room for much optimism - as this talk will demonstrate. Drawing inspiration from shortcomings of existing work, and from developments in CPU DBMSes (HyPer, VectorWise), we will lay out some key design features which should provide the next order-of-magnitude speedup: Richer query plan optimization with more expressive grammars; Compression and data layout; Fusion of operations and/or JITing; and an inclusive FOSS development model. We will (try) to convince ourselves that the interplay of these (especially the first three) is at least as important as their individual potential contribution.

[1] Breß, Sebastian, et al. "GPU-accelerated database systems: Survey and open challenges." Transactions on Large-Scale Data-and Knowledge-Centered Systems XV. Springer Berlin Heidelberg, 2014. 1-35. http://bit.ly/1rMOuZC

[2] Overtaking CPU DBMSes with a GPU in Whole-Query Analytic Processing with Parallelism-Friendly Execution Plan Optimization, Adnan Agbaria, David Minor, Natan Peterfreund, Eyal Rozenberg, and Ofer Rosenberg. http://www.adms-conf.org/2016/agbaria_adms16.pdf

Tuesday March 14, 2017
Start: 14.03.2017 10:00

CAB E 72

Speaker: Frank McSherry

Title: Monitoring motifs in graph streams

Abstract:

Imagine you are in charge of a high-volume stream of social interactions, and you would like to watch for certain graph structures in the stream of interactions. For example, Twitter recommends "who to follow" by looking for accounts followed by at least two accounts you follow, a structure which can be described by a four node graph. There can be a substantial number of these motifs in a graph, but what if  you only need to observe the changes as they happen, rather than enumerate all instances at once?

This work is an instance of the more general problem of maintaining cyclic (non-treelike) joins as the underlying relations change. We will first summarize recent work in worst-case optimal join evaluation (Ngo et al., 2014) which shows how to evaluate cyclic joins using resources asymptotically bounded by the largest possible output of the join (a  property standard trees of binary joins cannot satisfy). We then build up a dataflow version of this algorithm, extend it to efficiently respond to changes in its inputs, and describe and evaluate its implementation in timely dataflow*.  This project is joint work with Khaled Ammar and Semih Salihoglu, both > of University of Waterloo.

*: Timely dataflow's cycles are not required for this implementation, so it could also be suitable for other, less crazy streaming systems.

Bio: 

Frank McSherry is an independent scientist working on scalable  computation. His recent work focuses on data-parallel dataflow computation, in particular elevating their expressive power. He currently develops and maintains several related projects (https://github.com/frankmcsherry) and writes a somewhat sassy blog  (https://github.com/frankmcsherry/blog). Independently, he has also done foundational work on differential privacy, and continues to maintain an active presence in this community.

Thursday March 16, 2017
Start: 16.03.2017 10:00

CAB E 72

Low-latency Neutron Identification on FPGA for a Sterile Neutrino Experiment

Abstract

SoLid, located at SCK-CEN in Mol, Belgium, is a reactor antineutrino experiment at a very short aiming at the search for sterile neutrinos. It uses a novel approach using Lithium-6 sheets and PVT cubes as scintillators for tagging the Inverse Beta-Decay products (neutron and positron). Being located overground and close to the BR2 research reactor, the experiment faces a large amount of backgrounds. Efficient real-time low-latency background and noise rejection is essential in order to increase the signal-background ratio for precise oscillation measurement and decrease data production to a rate which can be handled by the online software. Therefore, a reliable distinction between the neutrons and background signals is crucial. This can be performed online with a dedicated firmware trigger. Applying machine learning metaheuristics, a peak counting algorithm and an algorithm measuring time over threshold have been identified as well-performing both in terms of Positive Predictive Value and False Positive Value, and have been implemented onto a Xilinx Artix-7 FPGA.

 

Shortbio

Lukas Arnold has studied Microelectronics at Fachhochschule Nordwestschweiz and, as visitor, at the University of Cambridge and Hochschule für Technik Rapperswil. Due to his strong interest in Microelectronics, he is currently about to graduate from an MSc in Particle Physics at the University of Bristol working on implementation on Machine Learning and FPGA development for a sterile neutrino experiment. He has worked for CERN, the University of Geneva, the University of Edinburgh, the World Bank and ABB in technical positions in relation to FPGA programming and Machine learning, mostly in conjunction with studies.

Tuesday March 21, 2017
Start: 21.03.2017 14:00

CAB E 72

Speaker: Rakesh Kumar

Title: Tailoring Server Architectures to Application Demands

 Abstract: 

The computing landscape is shifting from the traditional desktop computing to mobile-cloud computing model. In this new model, datacenters have emerged as the workhorses that do all the heavy-duty computations and serve as the backbone of mobile services. Datacenter applications are characterize by massive instruction footprints and typically operate on mutli tera/peta-byte datasets. Due to these huge instruction footprints and datasets, server processors spend significant amount of time waiting for instructions and data to arrive from cache/memory hierarchy. In this talk, I will present a storage-free instruction delivery mechanism and incorporation of 3D-stacked DRAM caches to tackle the problems of efficient instruction and data delivery in server applications.

Bio: 

Rakesh Kumar is a post-doctoral Research Associate in the School of Informatics at University of Edinburgh. His work focuses on scale-out servers, hardware/software co-designed processors, memory system, and run-time code generation and optimizations. He received his PhD from UPC Barcelona in 2014. During his internship at Intel Barcelona Research Center he developed memory controllers for Intel Skylake server architecture.

Friday March 24, 2017
Start: 24.03.2017 15:00

CAB E 72

Speaker: Christoph Kirsch (University of Salzburg)

Title:  Selfie: What is the Difference between Emulation and Virtualization?

Abstract:

This is work in progress. Selfie is educational software that implements a self-compiling compiler of a tiny C subset, a self-executing emulator of a tiny MIPS subset targeted by the compiler, and a self-hosting hypervisor that virtualizes the emulated machine. There is also a port to RISC-V supported by the official RISC-V toolchain. The code in selfie that handles context switching and virtual memory is shared by both the emulator and the hypervisor. In fact their only difference is that upon context switching the emulator interprets code while the hypervisor has the emulator on which it runs interpret code. We are currently trying to leverage that design for validating the functional equivalence of emulation and virtualization in test runs. The long term goal is to verify functional equivalence formally for all input programs. The talk provides an overview of the existing system and then focuses on current development and the challenges ahead. This is joint work with Armin Biere at JKU Linz.

 

Bio:

Christoph Kirsch is Professor at the Department of Computer Sciences of the University of Salzburg, Austria. He received his Dr.Ing. degree from Saarland University, Saarbrücken, Germany, in 1999 while at the Max Planck Institute for Computer Science. From 1999 to 2004 he worked as Postdoctoral Researcher at the Department of Electrical Engineering and Computer Sciences of the University of California, Berkeley. He later returned to Berkeley as Visiting Scholar (2008-2013) and Visiting Professor (2014) at the Department of Civil and Environmental Engineering as part of a collaborative research effort in Cyber-Physical Systems. His most recent research interests are in concurrent data structures, memory management, and so-called spatial programming. Dr. Kirsch co-invented embedded programming languages and systems such as Giotto, HTL, and the Embedded Machine, and more recently co-designed high-performance, multicore-scalable concurrent data structures and memory management systems. He co-founded the International Conference on Embedded Software (EMSOFT) and served as ACM SIGBED chair from 2011 until 2013 and ACM TODAES associate editor from 2011 until 2014. He is currently associate editor of IEEE TCAD.

 

Friday April 07, 2017
Start: 07.04.2017 12:15

CAB E 72

Lunch Seminar Talk by Aanjhan Ranganathan (ETH Zurich - System Security Group )

Title: Securing Next-generation Autonomous Cyber-physical Systems

Abstract:

The future is autonomous and cyber-physical systems will play a critical role in it. With their imminent integration and deployment into safety- and security-critical applications such as transportation, healthcare, and energy, it is important to ensure the resilience of these systems to attacks. Cyber-physical systems are a conglomeration of a variety of physical sensing, computing and communication technologies. Therefore, they are vulnerable to a wider range of attacks and security needs to become an integral part of the system’s design. In other words, there is a strong need to build secure sensing, computing and communication technologies without compromising on their performance guarantees.

In this talk, I will present my recent works on securing modern-day autonomous cyber-physical systems. First, location and time are critical to a wide-variety of applications (e.g., autonomous cars, drones) and today's systems are vulnerable to location spoofing attacks. I will introduce SPREE, the first spoofing resilient GPS receiver capable of limiting even the strongest of attackers known in the literature. Second, I will address the problem of guaranteeing timing properties in mixed-criticality systems in the scenario of partial hardware and software compromise. Third, I will briefly demonstrate the practical limits of isolation achievable on multi-core computing platforms which are today increasingly used in building autonomous systems. Finally, I will discuss open challenges and research opportunities that lie ahead enabling a secure and safe autonomous cyber-physical future.

Bio:

Aanjhan is currently a post-doctoral researcher in the System Security Group at ETH Zurich. He obtained his PhD in 2016 under the supervision of Prof. Dr. Srdjan Capkun. His research mostly revolves around the physical-layer security of wireless systems (e.g., secure localization and ranging, GPS security, (anti-) jamming techniques). His research on security of GPS was awarded the Swiss regional prize for innovative technolgies by the European Space Agency. His doctoral dissertation on “Physical-layer Techniques on Secure Proximity Verification and Localization Techniques” was awarded the ETH medal. In the past, he has worked on computer architectures, specifically, multiprocessor systems, cache coherency protocols and communication bus protocols. Prior to joining the System Security group at ETH Zurich, he worked at Robert Bosch GmbH's Car Multimedia Division "Blaupunkt" for over 3 years involved in research and development of embedded modules for top automotive manufacturers including Audi and Volkswagen.

Tuesday April 25, 2017
Start: 25.04.2017 09:30

Prof. Veljko Milutinovic will be giving a short course (lecture + hands-on tutorial) on Dataflow Supercomputing.

When:

25 April 2017:

  • 9:30-11:15 (Lecture)
  • 15:00-16:30 (Hands-on Tutorial)

26 April 2017:

  • 10:00-12:00 (Hands-on Tutorial)
  • 14:00-16:00 (Hands-on Tutorial)

Where: ML H 37.1

If interested in Hands-on Tutorial, please register by sending email to prof. Onur Mutlu (onur.mutlu@inf.ethz.ch) and Arash Tavakkol  (arash.tavakkol@inf.ethz.ch) since an individual account needs to be created for you to perform the hands-on tutorial activities on remote Maxeler machines.

Title: DataFlow SuperComputing for BigData

Abstract:

This short course analyses the essence of DataFlow SuperComputing, defines its advantages and sheds light on the related programming model. DataFlow computers, compared to ControlFlow computers, offer speedups of 20 to 200 (even 2000 for some applications), power reductions of about 20, and size reductions of also about 20. However, the programming paradigm is different, and has to be mastered. The paradigm is explained using Maxeler as an example, and light is shedded on the ongoing research in the field. Examples include CreditDerivatives and related banking applications, SignalProcessing, GeoPhysics, WeatherForecast, OilGas, DataEngineering, DataMining, SmartGrid, medical applications, etc. Also, a recent study from Tsinghua University in China is presented, which reveals that, for Shallow Water Weather Forecast (a BigData problem), on the 1U level, the Maxeler DataFlow machine is 14 times faster than the Tianhe machine, rated #1 on the Top 500 list (based on Linpack, which is a smalldata benchmark). Given enough time, a tutorial about the programming in space is also given, which is the programming paradigm used for the Maxeler dataflow machines (established in 2014 by Stanford, Imperial, Tsinghua, and the University of Tokyo). The introductory talk concludes with selected examples and a tool overview (appgallery.maxeler.com and webIDE.maxeler.com). A detailed tutorial on programming in space will be available after the introductory talk. Related hands-on activities will be performed by remote login (maxeler.mi.sanu.ac.rs).

About the Speaker:

Prof. Veljko Milutinovic (1951) received his PhD from the University of Belgrade, spent about a decade on various faculty positions in the USA (mostly at Purdue University), and was a co-designer of the DARPAs first GaAs RISC microprocessor. Later, for almost 3 decades, he taught and conducted research at the University of Belgrade, in EE, MATH, and PHY/CHEM. Now he serves as the Chairman of the Board for the Maxeler operation in Belgrade, Serbia. His research is mostly in datamining algorithms and dataflow computing, with the emphasis on mapping of data analytics algorithms onto fast energy efficient architectures. For 7 of his books, forewords were written by 7 different Nobel Laureates with whom he cooperated on his past industry sponsored projects. He has over 40 IEEE and ACM journal papers, over 400 Thomson-Reuters citations, and about 4000 Google Scholar citations.

Accompanying Papers and Textbooks:

Trifunovic, N., Milutinovic, V., et al, The Appgallery.Maxeler.com for BigData SuperComputing, Journal of Big Data, Springer, 2016.

Milutinovic, V., et al, Guide to DataFlow SuperComputing, Springer, 2015 (textbook).

Milutinovic, V., editor, Advances in Computers: DataFlow, Elsevier, 2015 (textbook).

Trifunovic, N., Milutinovic, V. et al, Paradigm Shift in SuperComputing: DataFlow vs ControlFlow, Journal of Big Data, 2015

Jovanovic, Z., Milutinovic, V., "FPGA Accelerator for Floating-Point Matrix Multiplication," The IET Computers and Digital Techniques Premium Award for 2014, Volume 6, Issue 4, 2012 (pp. 249-256).

Flynn, M., Mencer, O., Milutinovic, V., at al, Moving from PetaFlops to PetaData, Communications of the ACM, May 2013.

Trobec, R. Vasiljevic, R., Tomasevic, M., Milutinovic, V., et al, "Interconnection Networks for PetaComputing," ACM Computing Surveys, September 2016. ==================================================

Tuesday May 09, 2017
Start: 09.05.2017 17:30

HG G60

ETH “Science in Perspective” Talk Series: Internet and Trust

ABSTRACT:

A secure and reliable internet generates trust. Just how the internet creates trust is a matter for debate between ETH computer scientists and social scientists – for example, in a public session on 9 May 2017. Trust, it is sometimes said, is almost more important to the economy and society than money. Unlike money, trust is not a neutral unit of value and comparison, but rather a relationship quality. When you give someone your trust, you grant them a certain degree of latitude to act and in return expect certain benefits. In this respect, trust facilitates communication and the acquisition of information. More details: https://www.ethz.ch/en/news-and-events/eth-news/news/2017/05/how-does-tr...

----

 

Monday May 15, 2017
Start: 15.05.2017 17:15

Onur Mutlu will give his inaugural lecture entitled "Future Computing Architectures" on 15. May 2017 at 17:15 at the ETH Main Building F 30 (Auditorium Maximum).

Monday May 22, 2017
Start: 22.05.2017 16:15

ETH Zurich Distinguished Computer Science Colloquium

Talk by Marc Snir, University of Illinois at Urbana-Champaign, USA: High-Performance Computing in the Next Decade

Monday, 22 May 2017 16:15 - 17:15, CAB G 61

The talk is followed by an apéro in the CAB Foyer to which all colloquium attendees are invited.

Host: Torsten Hoefler

ABSTRACT:

The insatiable need of applications for more performance, as well as the desire for national prestige, is pushing several countries into ambitious exascale computing program. Exascale systems are likely to be deployed at the same time as when Moore’s Law is coming to an end. Two of the goals of the US exascale initiatives are: (1) Accelerating delivery of a capable exascale computing system that integrates hardware and software capability to deliver approximately 100 times the performance of current 10 petaflop systems across a range of applications representing government needs. (2) Establishing, over the next 15 years, a viable path forward for future HPC systems even after the limits of current semiconductor technology are reached (the “Post- Moore’s Law Era”). While there is reasonable confidence that the first goal can be achieved, it is much less clear that the second one is viable. As feature shrinking stops providing significant performance improvements, gains will have to come from new packaging, new architectures, and different software. Many of the gains will be “one-off” and specific to HPC, rather than resulting from the evolution of commodity technology. This will require significant changes in the HPC ecosystem. The talk will discuss these implications of the end of Moore’s Law on the future of HPC.

BIOGRAPHY:

Marc Snir is Michael Faiman Professor in the Department of Computer Science at the University of Illinois at Urbana-Champaign. He was Director of the Mathematics and Computer Science Division at the Argonne National Laboratory from 2011 to 2016 and head of the Computer Science Department at Illinois from 2001 to 2007. Until 2001 he was a senior manager at the IBM T. J. Watson Research Center where he led the Scalable Parallel Systems research group that was responsible for major contributions to the IBM SP scalable parallel system and to the IBM Blue Gene system. He is AAAS Fellow, ACM Fellow and IEEE Fellow. He has Erdos number 2 and is a mathematical descendant of Jacques Salomon Hadamard. He recently won the IEEE Award for Excellence in Scalable Computing and the IEEE Seymour Cray Computer Engineering Award.

Wednesday May 31, 2017
Start: 31.05.2017 17:15

Ce Zhang will give his inaugural lecture entitled "Data Sciences, Data Systems, and Data Services" on 31. May 2017 at 17:15 at the ETH Main Building F 30 (Auditorium Maximum).

Start: 31.05.2017 19:00

Event

The Compiler and Code Generation Social is a meetup to discuss compilation and code generation topics, with a special focus on LLVMclangPolly, and related projects. If you are interested in generating code for a variety of architectures, (static) program analyses for real world C/C++/OpenCL/CUDA programs, building your own programming language, register allocation and instruction selection, software hardening techniques, have an idea for a great optimization, or want to target GPUs ond FPGA, .... This event is for you!

Our primary focus are free discussions between interested people  (+ beer and food). This is a great opportunity to get and discuss project ideas or to just learn about what people at ETH and around Zurich are doing.

Registration

Please register to help us plan attendence.

Who

  • Anybody interested 
  • ETH students and staff
  • LLVM developers and enthusiasts external to ETH

When

31.05.2017, 19:00

Where

ETH Zurich, CAB, E72

Floorplan

The building closes at 19:00. If you are late, you need to call us to be let in. (We send out the number before the meeting).

What is LLVM?

LLVM is an open source project that provides a collection of modular compiler and toolchain technologies. It is centered around a modern SSA-based compiler around which an entire ecosystem of compiler technology was developed. Most well know is the clang C++ compiler, which is e.g. used to deploy iOS. Beyond this a diverse set of projects is developed under the umbrella of LLVM. These include code generators and assemblers for various interesting architectures, a jit compiler, a debugger, run-time libraries (C++ Standard Library, OpenMP, Opencl library), program sanity checkers, and many more. LLVM has itself grown out of a research project more than 10 years ago and is the base of many exciting research projects today:

https://scholar.google.ch/scholar?cites=7792455789532680075&as_sdt=2005&sciodt=0,5&hl=de

Contact

 

Monday June 19, 2017
Start: 19.06.2017 10:30

CAB E 72

 

Talk by Justin Levandoski (MSR Redmond): Storage and Indexing for Modern Hardware and the Cloud

 Abstract:

The deployment landscape for today's data management systems is vastly different than the 1980s and 90s, when many of the textbook database technology concepts were conceived. This landscape is diverse. On one hand, many systems run on servers with modern hardware consisting of large amounts of hardware parallelism, large amounts of main memory, and flash/SSDs. On the other hand, while hardware resources are vast, many system deployments take place within hosted cloud services that rely on heavy resource governance -- constraining things like memory and CPU provided to the database stacks -- in order to increase the number of instances packed on a single machine to decrease the hardware cost of running the service. This talk discusses work being done as part of the Deuteronomy project at MSR to redesign transactional database kernel technology for this landscape. I will first present the design details of the storage layer of Deuteronomy that uses the Bw-Tree/LLAMA. The Bw-tree is an highly-concurrent, in-memory B+-tree index that uses a latch-free copy-on-write technique for record updates as well as structure modifications (node splits and merges). LLAMA is the persistent storage layer that implements a log-structured page store that exploits the performance characteristics of flash/SSD and uses delta updates to reduce write amplification. I will then discuss two very different deployments of Bw-Tree/LLAMA within Microsoft that highlights its robust design: (1) as the index in Hekaton, the "scale up" in-memory OLTP engine in SQL Server and (2) as the storage engine in Azure CosmosDB, a fully hosted cloud storage service. Finally, I will highlight more forward-looking work on how to exploit new hardware features such as hardware transactional memory and non-volatile memory in the Deuteronomy storage engine.

Bio:

Justin Levandoski is a researcher in the database group at Microsoft Research. He is interested in a broad range of topics dealing with large-scale data management systems. His current interests include main-memory databases, database support for new hardware platforms, transaction processing, and cloud computing. His research has been commercialized in a number of Microsoft products, including the SQL Server Hekaton main-memory database engine, Azure CosmosDB, and Bing.

Start: 19.06.2017 17:00

PhD Defense: Darko Makreshanski

Title: Systems and Methods for Interactive Data Processing on Modern Hardware

Room: HG D22

Thursday July 13, 2017
Start: 13.07.2017 19:00

The LLVM Compiler and Code Generation Social is a meetup to discuss compilation and code generation topics, with a special focus on LLVM, clang, Polly, and related projects. If you are interested in generating code for a variety of architectures, (static) program analyses for real world C/C++/OpenCL/CUDA programs, building your own programming language, register allocation and instruction selection, software hardening techniques, have an idea for a great optimization, or want to target GPUs or FPGA, .... This event is for you!

Our primary focus are free discussions between interested people  (+ beer and food). This is a great opportunity to get and discuss project ideas or to just learn about what people at ETH and around Zurich are doing.

Registration

www.meetup.com/llvm-compiler-and-code-generation-socials-zurich/events/241141163/

Please register to help us plan attendence. 

Who

Anybody interested 

ETH students and staff

LLVM developers and enthusiasts external to ETH

When

13.07.2017, 19:00

We aim to arrange a meetup the second Thursday of a month

Where

ETH Zurich, CAB, E72

The building closes at 19:00. If you are late, you need to call us to be let in. (We send out the number before the meeting).

What is LLVM?

LLVM is an open source project that provides a collection of modular compiler and toolchain technologies. It is centered around a modern SSA-based compiler around which an entire ecosystem of compiler technology was developed. Most well know is the clang C++ compiler, which is e.g. used to deploy iOS. Beyond this a diverse set of projects is developed under the umbrella of LLVM. These include code generators and assemblers for various interesting architectures, a jit compiler, a debugger, run-time libraries (C++ Standard Library, OpenMP, Opencl library), program sanity checkers, and many more. LLVM has itself grown out of a research project more than 10 years ago and is the base of many exciting research projects today:

https://scholar.google.ch/scholar?cites=7792455789532680075&as_sdt=2005&...

 

 

 

Thursday July 20, 2017
Start: 20.07.2017 14:00
End: 20.07.2017 15:00

CAB G 51 

Talk by Stefano Ceri (Politecnico di Milano, Italy): Data-Driven Genomic Computing: Making Sense of the Signals from the Genome

Abstract:

Genomic computing is a new science focused on understanding the functioning of the genome, as a premise to fundamental discoveries in biology and medicine. Next Generation Sequencing (NGS) allows the production of the entire human genome sequence at a cost of about 1000 US $; many algorithms exist for the extraction of genome features, or "signals", including peaks (enriched regions), mutations, or gene expression (intensity of transcription activity). The missing gap is a system supporting data integration and exploration, giving a “biological meaning” to all the available information; such a system can be used, e.g., for better understanding cancer development. The GeCo Project (Data-Driven Genomic Computing, ERC Advanced Grant, 2016-2021) has the objective or revisiting genomic computing through the lens of basic data management, through models, languages, and instruments, focusing on genomic data integration. Starting from an abstract model, we developed a query language and data management system that can be used to query processed genomic data; the system employs internally the Spark engine, and prototypes can already be downloaded or accessed from our servers. During the five-years of the ERC project, the system will be enriched with data analysis tools and environments and will be made increasingly efficient. Among the objectives of the project, the creation of an “open source” repository of public data, available to biological and clinical research through queries, web services and search interfaces. At the end of the seminar, Pietro Pinoli (GeCo post-doc) will explain how biological applications are systematically addressed using GMQL integrated with Python, and Anna Bernasconi (GeCo PhD student) will describe the first results in the development of the public repository (integration of TCGA, Encode and Geo).

Bio:

Stefano Ceri is professor of Database Systems at the Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB) of Politecnico di Milano; he was visiting professor at the Computer Science Department of Stanford University (1983-1990). His research work covers four decades (1976-2016) and is generally concerned with extending data technologies in order to incorporate new features: distribution, object-orientation, rules, streaming data; with the advent of the Web, his research has been targeted towards the engineering of Web-based applications and to search systems. More recently he turned to crowd searching, to social media analytics, and to genomic computing. He is the recipient of two ERC Advanced Grants: "Search Computing (SeCo)" (2008-2013), focused upon the rank-aware integration of search engines in order to support multi-domain queries and “Data-Centered Genomic Computing (GeCo)” (2016-2021), focused upon new abstractions for querying and integrating genomic datasets. He is the recipient of the ACM-SIGMOD "Edward T. Codd Innovation Award" (New York, June 26, 2013), an ACM Fellow and a member of Academia Europaea.

Thursday August 10, 2017
Start: 10.08.2017 19:00

 

 

Event

 

 

The LLVM Compiler and Code Generation Social is a meetup to discuss compilation and code generation topics, with a special focus on LLVMclangPolly, and related projects. If you are interested in generating code for a variety of architectures, (static) program analyses for real world C/C++/OpenCL/CUDA programs, building your own programming language, register allocation and instruction selection, software hardening techniques, have an idea for a great optimization, or want to target GPUs or FPGA, .... This event is for you!

Our primary focus are free discussions between interested people  (+ beer and food). This is a great opportunity to get and discuss project ideas or to just learn about what people at ETH and around Zurich are doing.

 

Registration

Please register.

Who

  • Anybody interested 
  • ETH students and staff
  • LLVM developers and enthusiasts external to ETH

When

10.08.2017, 19:00

We aim to arrange a meetup the second Thursday of a months

Where

ETH Zurich, CAB, E72

Floorplan

The building closes at 19:00. If you are late, you need to call us to be let in. (We send out the number before the meeting).

What is LLVM?

LLVM is an open source project that provides a collection of modular compiler and toolchain technologies. It is centered around a modern SSA-based compiler around which an entire ecosystem of compiler technology was developed. Most well know is the clang C++ compiler, which is e.g. used to deploy iOS. Beyond this a diverse set of projects is developed under the umbrella of LLVM. These include code generators and assemblers for various interesting architectures, a jit compiler, a debugger, run-time libraries (C++ Standard Library, OpenMP, Opencl library), program sanity checkers, and many more. LLVM has itself grown out of a research project more than 10 years ago and is the base of many exciting research projects today:

https://scholar.google.ch/scholar?cites=7792455789532680075&as_sdt=2005&sciodt=0,5&hl=de

Contact

Tobias Grosser

 

 



 

 

Tuesday August 29, 2017

The Industry Day is an annually recurring event which showcases the research activities of ETH Zurich and offers a platform for industry to engage with ETH researchers. The event is free of charge.

Details and registration

The following talks will be given in the Information and Communication session (3rd session):

Prof. Jürg Leuthold, Optical communication

Prof. Onur Mutlu, Future computing and genome analysis platforms

Prof. Gunnar Rätsch, Analysis and modelling of biomedical data

Prof. Timothy Roscoe, Online modelling of enterprise datacenter behavior

ETH spin-off Veezoo, Platform for data exploration

Wednesday August 30, 2017
Start: 30.08.2017 11:00

CAB E 72

Talk by Ganesh Ananthanarayanan (Microsoft Research)

TITLE: Taming the Video Star! Real-time Video Analytics at Scale

ABSTRACT:

Video cameras are pervasively deployed for security and smart city scenarios, with millions of them in large cities worldwide. Achieving the potential of these cameras requires efficiently analyzing the live videos in real-time. In this talk, I’ll describe VideoStorm, a video analytics system that processes thousands of video analytics queries on live video streams over large clusters. Given the high costs of vision processing, resource management is crucial. We consider two key characteristics of video analytics: resource-quality tradeoff with multi-dimensional configurations, and variety in quality and lag goals. VideoStorm’s offline profiler generates query resource-quality profile, while its online scheduler allocates resources to queries to maximize performance on quality and lag, in contrast to the commonly used fair sharing of resources in clusters. Deployment on an Azure cluster of 101 machines shows improvement by as much as 80% in quality of real-world queries and 7× better lag, processing video from operational traffic cameras. VideoStorm has also been powering our deployment at the City of Bellevue, WA for analyzing live traffic camera feeds.

BIO:

Ganesh Ananthanarayanan is a Researcher at Microsoft Research. His research interests are broadly in systems & networking, with recent focus on cloud computing and large scale data analytics systems, video analytics, and Internet performance. He has published over 30 papers in the top-tier computing venues such as USENIX OSDI, ACM SIGCOMM and USENIX NSDI. His work on “Video Analytics for Vision Zero” on analyzing traffic camera feeds won the Institute of Transportation Engineers 2017 Achievement Award. Technology from his work have contributed to Microsoft’s cloud and online products like the Azure Cloud, Cosmos (Microsoft’s big data system), and Skype. He is also a member of the ACM Future of Computing Academy. Prior to joining Microsoft Research, he completed his Ph.D. at UC Berkeley in Dec 2013 working with Prof. Ion Stoica, where he was also a recipient of the UC Berkeley Regents Fellowship. More details about Ganesh’s work can be found here: http://aka.ms/ganesh

Monday September 18, 2017
Monday October 16, 2017
Start: 16.10.2017 11:00

CAB E 72

Talk by Yishai Oltchik (Hebrew University of Jerusalem)

Title: Network Topologies and Inevitable Contention

Abstract:

Network topologies can have significant effect on the execution costs of parallel algorithms due to inter-processor communication. For particular combinations of computations and network topologies, costly network contention may inevitably become a bottleneck, even if algorithms are optimally designed so that each processor communicates as little as possible. We obtain novel contention lower bounds that are functions of the network and the computation graph parameters. For several combinations of fundamental computations and common network topologies, our new analysis improves upon previous per-processor lower bounds which only specify the number of words communicated by the busiest individual processor. We consider torus and mesh topologies, universal fat-trees, and hypercubes; algorithms covered include classical matrix multiplication and direct numerical linear algebra, fast matrix multiplication algorithms, programs that reference arrays, N-body computations, and the FFT. For example, we show that fast matrix multiplication algorithms (e.g., Strassen’s) running on a 3D torus will suffer from contention bottlenecks. On the other hand, this network is likely sufficient for a classical matrix multiplication algorithm. Our new lower bounds are matched by existing algorithms only in very few cases, leaving many open problems for network and algorithmic design.

Biography:

Yishai Oltchik is currently a MSc student at the Hebrew University of Jerusalem under the supervision of Oded Schwartz, researching parallel computation and HPC. His primary research interests are in the fields of network topologies and parallel algorithms.

Thursday November 09, 2017
Start: 09.11.2017 10:00

CAB E72

Brian Gold (Pure Storage)

Title: Accelerating scale-out file systems with hardware/software co-design

Abstract:

Modern file systems can be viewed as specialized database applications, enabling features such as snapshots, compression, replication, and more. As data volumes and performance demands continue to grow, file-system designers have turned to scale-out architectures and, therefore, suffer the joys and pains of distributed database systems. In this talk we will describe several of the key insights behind Pure Storage's FlashBlade, a scale-out file and object storage system that achieves scalability and performance through deep hardware/software co-design.

Bio:

Brian Gold is an engineering director at Pure Storage and part of the founding team for FlashBlade, Pure’s scale-out, all-flash file and object storage platform. He’s contributed to nearly every part of the FlashBlade architecture and development from inception to production, but fortunately most of his code has been rewritten by others. Brian received a PhD from Carnegie Mellon University, focusing on computer architecture and resilient computing. ===========

Start: 09.11.2017 19:00

LLVM Compiler and Code Generation Social

 

Details and registration at: www.meetup.com/llvm-compiler-and-code-generation-socials-zurich/events/242409252/

Friday November 24, 2017
Start: 24.11.2017 12:15

 CAB E 72

Sandhya Dwarkadas (University of Rochester/invited professor at EPFL) 

Title: Performance Isolation on Modern Multi-Socket Systems

Abstract:  

Recognizing that applications are rarely executed in isolation today, I will discuss some practical challenges in making best use of available hardware and our approach to addressing these challenges. I will describe two independent and complementary control mechanisms using low-overhead hardware performance counters that we have developed: a sharing- and resource-aware mapper (SAM) to effect task placement with the goal of localizing shared data communication and minimizing resource contention based on the offered load; and an application parallelism manager (MAP) that controls the offered load with the goal of improving system parallel efficiency. Our results emphasize the need for low-overhead monitoring of application behavior under changing environmental condititons in order to adapt to environment and application behavior changes. If time permits, I will also outline additional work on memory management design that eliminates address translation redundancy via appropriate sharing.

Bio:

Sandhya Dwarkadas is the Albert Arendt Hopeman Professor and Chair of Computer Science at the University of Rochester, with a secondary appointment in Electrical and Computer Engineering. She is currently on sabbatical as an invited professor at EPFL. She was named an IEEE fellow in 2017 for her contributions to shared memory and reconfigurability. Her research is targeted at both the hardware and software layers of computing systems and especially at the boundary, with a particular focus on the challenges of making coordination and communication efficient in parallel and distributed systems. She is co-inventor on 12 granted U.S. patents. She was program chair for ASPLOS (International Conference on Architectural Support for Programming Languages and Operating Systems) 2015. She is currently a board member on Computing Research Association's Committee on the Status of Women in Computing Research (CRA-W).

URL: http://www.cs.rochester.edu/u/sandhya

Monday December 04, 2017
Start: 04.12.2017 16:00

HG D22

Gerd Zellweger - PhD Defense

 Title: On the Construction of Dynamic and Adaptive Operating Systems

Committee:

  • Timothy Roscoe
  • Gustavo Alonso
  • Jonathan Appavoo (Boston University)

 

Friday December 08, 2017
Start: 08.12.2017 12:15

CAB G 61

Kaveh Razavi (Vrije Universiteit Amsterdam)

Title: The Sad State of Software on Unreliable and Leaky Hardware

Abstract:

Hardware that we use today is unreliable and leaky. Bit flips plague a substantial part of the memory hardware that we use today and there are a variety of side channels that leak sensitive information about the system. In this talk, I will briefly talk about how we turned Rowhammer bit flips into practical exploitation vectors compromising browsers, clouds and mobile phones. I will then talk about a new side-channel attack that uses the traces that the memory management unit of the processor leaves in its data/instruction caches to derandomize secret pointers from JavaScript. This attack is very powerful: it breaks address-space layout randomization (ASLR) in the browser on all the 22 modern CPU architectures that we tried in only tens of seconds and it is not easy to fix. It is time to rethink our reliance on ASLR as a basic security mechanism in sandboxed environments such as JavaScript.

Bio:

Kaveh Razavi is starting as an assistant professor in the VUSec group of Vrije Universiteit Amsterdam next year. Besides building systems, he is currently mostly interested in the security implications of unreliable and leaky general-purpose hardware. He regularly publishes at top systems and systems security venues and his research has won multiple industry and academic awards including different Pwnies and the CSAW applied best research paper. In the past, he has built network and storage stacks for rack-scale computers at Microsoft Research (2014-2015), worked on the scalability issues of cloud virtual machines for his PhD (2012-2015) and hacked on Barrelfish as a master student (2010-2011)!

Monday December 11, 2017
Start: 11.12.2017 16:15

CAB G 61 

Distinguished Computer Science Colloquium:

Subhasish Mitra, Stanford University, California, USA

Transforming Nanodevices into Nanosystems: The N3XT 1,000X

Host: Prof. Onur Mutlu

ABSTRACT:

Coming generations of information technology will process unprecedented amounts of loosely-structured data, including streaming video and audio, natural languages, real-time sensor readings, contextual environments, or even brain signals. The computation demands of these abundant-data applications (e.g., deep learning) far exceed the capabilities of today’s computing systems, and cannot be met by isolated improvements in transistor technologies, memories, or integrated circuit (IC) architectures alone. Transformative nanosystems, which leverage the unique properties of emerging nanotechnologies to create new IC architectures, are required to deliver unprecedented functionality, performance and energy efficiency. However, emerging nanomaterials and nanodevices face major obstacles such as inherent imperfections and variations. Thus, realizing working circuits, let alone transformative nanosystems, has been infeasible. The N3XT (Nano-Engineered Computing Systems Technology) approach overcomes these challenges through recent innovations across the computing stack: (a) new logic devices using nanomaterials such as one-dimensional carbon nanotubes (and two-dimensional semiconductors) for high performance and energy efficiency; (b) high-density non-volatile resistive and magnetic memories; (c) ultra-dense (e.g., monolithic) three-dimensional integration of thin layers of logic and memory with fine-grained connectivity; (d) new IC architectures for computation immersed in memory; and, (e) new materials technologies and their integration for efficient heat removal. N3XT hardware prototypes represent leading examples of transforming the basic science of nanomaterials and nanodevices into actual nanosystems. Compared to conventional (2D) systems, N3XT architectures promise to improve the energy efficiency of abundant-data applications significantly, in the range of three orders of magnitude. Such massive benefits enable new frontiers of applications for a wide range of computing systems, from embedded systems to the cloud.

BIOGRAPHY:

Subhasish Mitra is Professor of Electrical Engineering and of Computer Science at Stanford University, where he directs the Stanford Robust Systems Group and co-leads the Computation focus area of the Stanford SystemX Alliance. He is also a faculty member of the Stanford Neurosciences Institute. Before joining the Stanford faculty, he was a Principal Engineer at Intel Corporation. Prof. Mitra's research interests range broadly across robust computing, nanosystems, VLSI design, CAD, validation and test, and neurosciences. He, jointly with his students and collaborators, demonstrated the first carbon nanotube computer and the first 3D Nanosystem with computation immersed in memory. These demonstrations received wide-spread recognitions (cover of NATURE, research highlight to the United States Congress by the National Science Foundation, highlight as "important, scientific breakthrough" by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Public Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post and numerous others worldwide). His earlier work on X-Compact test compression has been key to cost-effective manufacturing and high-quality testing of a vast majority of electronic systems. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools. Prof. Mitra's honors include the ACM SIGDA/IEEE CEDA Richard Newton Technical Impact Award in Electronic Design Automation (a test of time honor), the Semiconductor Research Corporation's Technical Excellence Award, the Intel Achievement Award (Intel’s highest corporate honor), and the Presidential Early Career Award for Scientists and Engineers from the White House (the highest United States honor for early-career outstanding scientists and engineers). He and his students published several award-winning papers at major venues: IEEE/ACM Design Automation Conference, IEEE International Solid-State Circuits Conference, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, and the Symposium on VLSI Technology. At Stanford, he has been honored several times by graduating seniors "for being important to them during their time at Stanford." Prof. Mitra served on the Defense Advanced Research Projects Agency's (DARPA) Information Science and Technology Board as an invited member. He is a Fellow of the ACM and the IEEE.

Friday December 15, 2017
Start: 15.12.2017 12:00

CAB E 72

Kevin Chang (Carnegie Mellon University)

Title: Understanding and Improving the Latency of DRAM-Based Memory Systems

Abstract:

Over the past two decades, the storage capacity and access bandwidth of main memory have improved tremendously, by 128x and 20x, respectively. These improvements are mainly due to the continuous technology scaling of DRAM (dynamic random-access memory), which has been used as the physical substrate for main memory. In stark contrast with capacity and bandwidth, DRAM latency has remained almost constant, reducing by only 1.3x in the same time frame. Therefore, long DRAM latency continues to be a critical performance bottleneck in modern systems. Increasing core counts, and the emergence of increasingly more data-intensive and latency-critical applications further stress the importance of providing low-latency memory accesses. In this talk, we will identify three main problems that contribute significantly to long latency of DRAM accesses. To address these problems, we show that (1) augmenting DRAM chip architecture with simple and low-cost features, and (2) developing a better understanding of manufactured DRAM chips together leads to significant memory latency reduction. Our new proposals significantly improve both system performance and energy efficiency.

Bio:

Kevin Chang is a recent Ph.D. graduate in electrical and computer engineering from Carnegie Mellon University, where he's advised by Prof. Onur Mutlu. He is broadly interested in computer architecture, large-scale systems, and emerging technologies. Specifically, his graduate research focuses on improving performance and energy-efficiency of memory systems. He will join Facebook as a research scientist. He was a recipient of the SRC and Intel fellowship.

Thursday December 21, 2017
Start: 21.12.2017 17:00

Title: Building Distributed Storage with Specialized Hardware

Committee:

  • Gustavo Alonso
  • Timothy Roscoe
  • Torsten Hoefler
  • Ken Eguro (MSR Redmond, USA)  

Room: HG D 22

Sunday January 21, 2018
Start: 21.01.2018 00:00
End: 21.01.2018 00:00
Monday February 19, 2018
Start: 19.02.2018 00:00
Thursday February 22, 2018
Start: 22.02.2018 11:00

 

COMPASS: Computing Platforms Seminar Series

CAB E 72

Speaker : Ioannis Koltsidas (IBM Research Zurich)


Title:
System software for commodity solid-state storage

 

 

 

 

Abstract:

The high-performance storage landscape is being shaped by three main developments: a) Flash memories are scaling to extreme densities (e.g., 3D-TLC, QLC), b) new storage devices offer single-digit microsecond latencies (e.g., SSDs based on 3D-Xpoint memory), c) new standards provide high-performance, efficient access to local (e.g., NVMe) and remote storage (e.g., NVMeoF).

In this talk we present our work on building systems to maximize the benefits of new technologies, targeting commodity hardware environments such as cloud datacenters. Specifically, we focus on: a) Improving performance and endurance of low-cost Flash via a host translation layer, and b) exploiting low-latency NVM devices to reduce the cost and increase the scalability of systems that would otherwise rely on large amounts of DRAM.

Key ingredients in our stack include a storage virtualization layer, an efficient Key-Value storage engine built specifically for the new types of media, and a novel task-based I/O runtime system that enables CPU-efficient, high performance access to storage in a programmer-friendly way. We present an overview of these technologies along with lessons learned while building them, as well as experimental evidence that demonstrate their applicability.

Shortbio:

Ioannis (Yannis) Koltsidas is a Research Staff Member in the Cloud Computing Infrastructure department at the IBM Research Lab in Zurich, Switzerland. In his current role he is leading a team of researchers doing research on next-generation Flash-enabled storage systems, exploitation of Flash memory in host servers, as well as applications of Storage-class Memories, such as Phase-Change Memory. His interests also include distributed scale-out file storage (GPFS, HDFS) and extensions thereof based on open-format magnetic tape. Some of the latest projects he has been involved in include the IBM FlashSystem, the IBM Easy Tier Server for the DS8000 series and the IBM LTFS Enterprise Edition.

Previously, Ioannis received his PhD in Computer Science from the University of Edinburgh, where he was a member of the Database Group at the School of Informatics. His research was supervised by Prof. Stratis Viglas. The focus of his thesis, titled "Flashing Up The Storage Hierarchy", was on database systems and data-intensive systems in general that employ novel storage media, such as NAND Flash SSDs and use novel algorithms and data structures to boost I/O performance. Prior to that, Ioannis completed his undergraduate studies at the Electrical and Computer Engineering Department of the National Techinical University of Athens (NTUA) in Athens, Greece, where he majored in Computer Science. =========

 

COMPASS Talks

Friday February 23, 2018
Start: 23.02.2018 12:15

Lunch Seminar - Spring 2018