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Monday September 18, 2017
Monday October 16, 2017
Start: 16.10.2017 11:00

CAB E 72

Talk by Yishai Oltchik (Hebrew University of Jerusalem)

Title: Network Topologies and Inevitable Contention

Abstract:

Network topologies can have significant effect on the execution costs of parallel algorithms due to inter-processor communication. For particular combinations of computations and network topologies, costly network contention may inevitably become a bottleneck, even if algorithms are optimally designed so that each processor communicates as little as possible. We obtain novel contention lower bounds that are functions of the network and the computation graph parameters. For several combinations of fundamental computations and common network topologies, our new analysis improves upon previous per-processor lower bounds which only specify the number of words communicated by the busiest individual processor. We consider torus and mesh topologies, universal fat-trees, and hypercubes; algorithms covered include classical matrix multiplication and direct numerical linear algebra, fast matrix multiplication algorithms, programs that reference arrays, N-body computations, and the FFT. For example, we show that fast matrix multiplication algorithms (e.g., Strassen’s) running on a 3D torus will suffer from contention bottlenecks. On the other hand, this network is likely sufficient for a classical matrix multiplication algorithm. Our new lower bounds are matched by existing algorithms only in very few cases, leaving many open problems for network and algorithmic design.

Biography:

Yishai Oltchik is currently a MSc student at the Hebrew University of Jerusalem under the supervision of Oded Schwartz, researching parallel computation and HPC. His primary research interests are in the fields of network topologies and parallel algorithms.

Thursday November 09, 2017
Start: 09.11.2017 10:00

CAB E72

Brian Gold (Pure Storage)

Title: Accelerating scale-out file systems with hardware/software co-design

Abstract:

Modern file systems can be viewed as specialized database applications, enabling features such as snapshots, compression, replication, and more. As data volumes and performance demands continue to grow, file-system designers have turned to scale-out architectures and, therefore, suffer the joys and pains of distributed database systems. In this talk we will describe several of the key insights behind Pure Storage's FlashBlade, a scale-out file and object storage system that achieves scalability and performance through deep hardware/software co-design.

Bio:

Brian Gold is an engineering director at Pure Storage and part of the founding team for FlashBlade, Pure’s scale-out, all-flash file and object storage platform. He’s contributed to nearly every part of the FlashBlade architecture and development from inception to production, but fortunately most of his code has been rewritten by others. Brian received a PhD from Carnegie Mellon University, focusing on computer architecture and resilient computing. ===========

Start: 09.11.2017 19:00

LLVM Compiler and Code Generation Social

 

Details and registration at: www.meetup.com/llvm-compiler-and-code-generation-socials-zurich/events/242409252/

Friday November 24, 2017
Start: 24.11.2017 12:15

 CAB E 72

Sandhya Dwarkadas (University of Rochester/invited professor at EPFL) 

Title: Performance Isolation on Modern Multi-Socket Systems

Abstract:  

Recognizing that applications are rarely executed in isolation today, I will discuss some practical challenges in making best use of available hardware and our approach to addressing these challenges. I will describe two independent and complementary control mechanisms using low-overhead hardware performance counters that we have developed: a sharing- and resource-aware mapper (SAM) to effect task placement with the goal of localizing shared data communication and minimizing resource contention based on the offered load; and an application parallelism manager (MAP) that controls the offered load with the goal of improving system parallel efficiency. Our results emphasize the need for low-overhead monitoring of application behavior under changing environmental condititons in order to adapt to environment and application behavior changes. If time permits, I will also outline additional work on memory management design that eliminates address translation redundancy via appropriate sharing.

Bio:

Sandhya Dwarkadas is the Albert Arendt Hopeman Professor and Chair of Computer Science at the University of Rochester, with a secondary appointment in Electrical and Computer Engineering. She is currently on sabbatical as an invited professor at EPFL. She was named an IEEE fellow in 2017 for her contributions to shared memory and reconfigurability. Her research is targeted at both the hardware and software layers of computing systems and especially at the boundary, with a particular focus on the challenges of making coordination and communication efficient in parallel and distributed systems. She is co-inventor on 12 granted U.S. patents. She was program chair for ASPLOS (International Conference on Architectural Support for Programming Languages and Operating Systems) 2015. She is currently a board member on Computing Research Association's Committee on the Status of Women in Computing Research (CRA-W).

URL: http://www.cs.rochester.edu/u/sandhya

Monday December 04, 2017
Start: 04.12.2017 16:00

HG D22

Gerd Zellweger - PhD Defense

 Title: On the Construction of Dynamic and Adaptive Operating Systems

Committee:

  • Timothy Roscoe
  • Gustavo Alonso
  • Jonathan Appavoo (Boston University)

 

Friday December 08, 2017
Start: 08.12.2017 12:15

CAB G 61

Kaveh Razavi (Vrije Universiteit Amsterdam)

Title: The Sad State of Software on Unreliable and Leaky Hardware

Abstract:

Hardware that we use today is unreliable and leaky. Bit flips plague a substantial part of the memory hardware that we use today and there are a variety of side channels that leak sensitive information about the system. In this talk, I will briefly talk about how we turned Rowhammer bit flips into practical exploitation vectors compromising browsers, clouds and mobile phones. I will then talk about a new side-channel attack that uses the traces that the memory management unit of the processor leaves in its data/instruction caches to derandomize secret pointers from JavaScript. This attack is very powerful: it breaks address-space layout randomization (ASLR) in the browser on all the 22 modern CPU architectures that we tried in only tens of seconds and it is not easy to fix. It is time to rethink our reliance on ASLR as a basic security mechanism in sandboxed environments such as JavaScript.

Bio:

Kaveh Razavi is starting as an assistant professor in the VUSec group of Vrije Universiteit Amsterdam next year. Besides building systems, he is currently mostly interested in the security implications of unreliable and leaky general-purpose hardware. He regularly publishes at top systems and systems security venues and his research has won multiple industry and academic awards including different Pwnies and the CSAW applied best research paper. In the past, he has built network and storage stacks for rack-scale computers at Microsoft Research (2014-2015), worked on the scalability issues of cloud virtual machines for his PhD (2012-2015) and hacked on Barrelfish as a master student (2010-2011)!

Monday December 11, 2017
Start: 11.12.2017 16:15

CAB G 61 

Distinguished Computer Science Colloquium:

Subhasish Mitra, Stanford University, California, USA

Transforming Nanodevices into Nanosystems: The N3XT 1,000X

Host: Prof. Onur Mutlu

ABSTRACT:

Coming generations of information technology will process unprecedented amounts of loosely-structured data, including streaming video and audio, natural languages, real-time sensor readings, contextual environments, or even brain signals. The computation demands of these abundant-data applications (e.g., deep learning) far exceed the capabilities of today’s computing systems, and cannot be met by isolated improvements in transistor technologies, memories, or integrated circuit (IC) architectures alone. Transformative nanosystems, which leverage the unique properties of emerging nanotechnologies to create new IC architectures, are required to deliver unprecedented functionality, performance and energy efficiency. However, emerging nanomaterials and nanodevices face major obstacles such as inherent imperfections and variations. Thus, realizing working circuits, let alone transformative nanosystems, has been infeasible. The N3XT (Nano-Engineered Computing Systems Technology) approach overcomes these challenges through recent innovations across the computing stack: (a) new logic devices using nanomaterials such as one-dimensional carbon nanotubes (and two-dimensional semiconductors) for high performance and energy efficiency; (b) high-density non-volatile resistive and magnetic memories; (c) ultra-dense (e.g., monolithic) three-dimensional integration of thin layers of logic and memory with fine-grained connectivity; (d) new IC architectures for computation immersed in memory; and, (e) new materials technologies and their integration for efficient heat removal. N3XT hardware prototypes represent leading examples of transforming the basic science of nanomaterials and nanodevices into actual nanosystems. Compared to conventional (2D) systems, N3XT architectures promise to improve the energy efficiency of abundant-data applications significantly, in the range of three orders of magnitude. Such massive benefits enable new frontiers of applications for a wide range of computing systems, from embedded systems to the cloud.

BIOGRAPHY:

Subhasish Mitra is Professor of Electrical Engineering and of Computer Science at Stanford University, where he directs the Stanford Robust Systems Group and co-leads the Computation focus area of the Stanford SystemX Alliance. He is also a faculty member of the Stanford Neurosciences Institute. Before joining the Stanford faculty, he was a Principal Engineer at Intel Corporation. Prof. Mitra's research interests range broadly across robust computing, nanosystems, VLSI design, CAD, validation and test, and neurosciences. He, jointly with his students and collaborators, demonstrated the first carbon nanotube computer and the first 3D Nanosystem with computation immersed in memory. These demonstrations received wide-spread recognitions (cover of NATURE, research highlight to the United States Congress by the National Science Foundation, highlight as "important, scientific breakthrough" by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Public Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post and numerous others worldwide). His earlier work on X-Compact test compression has been key to cost-effective manufacturing and high-quality testing of a vast majority of electronic systems. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools. Prof. Mitra's honors include the ACM SIGDA/IEEE CEDA Richard Newton Technical Impact Award in Electronic Design Automation (a test of time honor), the Semiconductor Research Corporation's Technical Excellence Award, the Intel Achievement Award (Intel’s highest corporate honor), and the Presidential Early Career Award for Scientists and Engineers from the White House (the highest United States honor for early-career outstanding scientists and engineers). He and his students published several award-winning papers at major venues: IEEE/ACM Design Automation Conference, IEEE International Solid-State Circuits Conference, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, and the Symposium on VLSI Technology. At Stanford, he has been honored several times by graduating seniors "for being important to them during their time at Stanford." Prof. Mitra served on the Defense Advanced Research Projects Agency's (DARPA) Information Science and Technology Board as an invited member. He is a Fellow of the ACM and the IEEE.

Friday December 15, 2017
Start: 15.12.2017 12:00

CAB E 72

Kevin Chang (Carnegie Mellon University)

Title: Understanding and Improving the Latency of DRAM-Based Memory Systems

Abstract:

Over the past two decades, the storage capacity and access bandwidth of main memory have improved tremendously, by 128x and 20x, respectively. These improvements are mainly due to the continuous technology scaling of DRAM (dynamic random-access memory), which has been used as the physical substrate for main memory. In stark contrast with capacity and bandwidth, DRAM latency has remained almost constant, reducing by only 1.3x in the same time frame. Therefore, long DRAM latency continues to be a critical performance bottleneck in modern systems. Increasing core counts, and the emergence of increasingly more data-intensive and latency-critical applications further stress the importance of providing low-latency memory accesses. In this talk, we will identify three main problems that contribute significantly to long latency of DRAM accesses. To address these problems, we show that (1) augmenting DRAM chip architecture with simple and low-cost features, and (2) developing a better understanding of manufactured DRAM chips together leads to significant memory latency reduction. Our new proposals significantly improve both system performance and energy efficiency.

Bio:

Kevin Chang is a recent Ph.D. graduate in electrical and computer engineering from Carnegie Mellon University, where he's advised by Prof. Onur Mutlu. He is broadly interested in computer architecture, large-scale systems, and emerging technologies. Specifically, his graduate research focuses on improving performance and energy-efficiency of memory systems. He will join Facebook as a research scientist. He was a recipient of the SRC and Intel fellowship.

Thursday December 21, 2017
Start: 21.12.2017 17:00

Title: Building Distributed Storage with Specialized Hardware

Committee:

  • Gustavo Alonso
  • Timothy Roscoe
  • Torsten Hoefler
  • Ken Eguro (MSR Redmond, USA)  

Room: HG D 22

Sunday January 21, 2018
Start: 21.01.2018 00:00
End: 21.01.2018 00:00
Monday February 19, 2018
Start: 19.02.2018 00:00
Thursday February 22, 2018
Start: 22.02.2018 11:00

 

COMPASS: Computing Platforms Seminar Series

CAB E 72

Speaker : Ioannis Koltsidas (IBM Research Zurich)


Title:
System software for commodity solid-state storage

 

 

 

 

Abstract:

The high-performance storage landscape is being shaped by three main developments: a) Flash memories are scaling to extreme densities (e.g., 3D-TLC, QLC), b) new storage devices offer single-digit microsecond latencies (e.g., SSDs based on 3D-Xpoint memory), c) new standards provide high-performance, efficient access to local (e.g., NVMe) and remote storage (e.g., NVMeoF).

In this talk we present our work on building systems to maximize the benefits of new technologies, targeting commodity hardware environments such as cloud datacenters. Specifically, we focus on: a) Improving performance and endurance of low-cost Flash via a host translation layer, and b) exploiting low-latency NVM devices to reduce the cost and increase the scalability of systems that would otherwise rely on large amounts of DRAM.

Key ingredients in our stack include a storage virtualization layer, an efficient Key-Value storage engine built specifically for the new types of media, and a novel task-based I/O runtime system that enables CPU-efficient, high performance access to storage in a programmer-friendly way. We present an overview of these technologies along with lessons learned while building them, as well as experimental evidence that demonstrate their applicability.

Shortbio:

Ioannis (Yannis) Koltsidas is a Research Staff Member in the Cloud Computing Infrastructure department at the IBM Research Lab in Zurich, Switzerland. In his current role he is leading a team of researchers doing research on next-generation Flash-enabled storage systems, exploitation of Flash memory in host servers, as well as applications of Storage-class Memories, such as Phase-Change Memory. His interests also include distributed scale-out file storage (GPFS, HDFS) and extensions thereof based on open-format magnetic tape. Some of the latest projects he has been involved in include the IBM FlashSystem, the IBM Easy Tier Server for the DS8000 series and the IBM LTFS Enterprise Edition.

Previously, Ioannis received his PhD in Computer Science from the University of Edinburgh, where he was a member of the Database Group at the School of Informatics. His research was supervised by Prof. Stratis Viglas. The focus of his thesis, titled "Flashing Up The Storage Hierarchy", was on database systems and data-intensive systems in general that employ novel storage media, such as NAND Flash SSDs and use novel algorithms and data structures to boost I/O performance. Prior to that, Ioannis completed his undergraduate studies at the Electrical and Computer Engineering Department of the National Techinical University of Athens (NTUA) in Athens, Greece, where he majored in Computer Science. =========

 

COMPASS Talks

Friday February 23, 2018
Start: 23.02.2018 12:15

Lunch Seminar - Spring 2018

Thursday March 01, 2018
Start: 01.03.2018 16:00

 

COMPASS: Computing Platforms Seminar Series

CAB E 72

Speaker: Saughata Ghose, Carnegie Mellon University

Title: How Safe Is Your Storage? A Look at the Reliability and Vulnerability of Modern Solid-State Drives

 

 

 

 

Abstract:

We live in an increasingly data-driven world, where we process and store a much greater amount of data, and we need to reliably keep this data around for a very long time. Today, solid-state drives (SSDs) made of NAND flash memory have become a popular choice for storage, as SSDs offer high storage density and high performance at a low cost. To keep up with consumer demand, manufacturers have been using a number of techniques to increase the density of SSDs. Unfortunately, this density scaling introduces new types of errors that can seriously affect the reliability of the data, and in turn significantly reduce the lifetime of the SSD.

In this talk, I will cover several issues that we have found which affect data reliability and vulnerability on modern SSDs available on the market today. I will explore two such issues in depth, along with solutions we have developed to mitigate or eliminate these issues. First, I will discuss read disturb errors, where reading one piece of data from an SSD can introduce errors into unread pieces of data. Second, I will discuss program interference errors, where writing one piece of data to an SSD can introduce errors both into other pieces of data and to data that has yet to be written. Notably, our findings show that the predominant solution adopted by industry to mitigate program interference actually introduces other interference errors, and exposes security exploits that can be used by malicious applications. For both issues, I will discuss solutions that we have developed based on these error types, which can buy back much of the lost lifetime, and which can eliminate the security exploits.

Shortbio:

Saugata Ghose is a Systems Scientist in the Department of Electrical and Computer Engineering at Carnegie Mellon University. He received dual B.S. degrees in computer science and in computer engineering from Binghamton University, State University of New York, and the M.S. and Ph.D. degrees from Cornell University, where he was the recipient of the NDSEG Fellowship and the ECE Director’s Ph.D. Teaching Assistant Award. He received the Best Paper Award from the DFRWS-EU conference in 2017, for his work on recovering data from solid-state drives. His current research interests include application- and system-aware memory and storage systems, virtual memory management, architectural solutions for large-scale systems, GPUs, and emerging memory technologies. For more information, see his website at https://ece.cmu.edu/~saugatag/.

COMPASS Talks

Friday March 02, 2018
Start: 02.03.2018 10:00

Speaker: Brad Beckmann (AMD Research)

Title: Processor Design for Exascale Computing

Date and Venue: Friday 2nd of March, 2018, at 10:00am, CAB E 72

Abstract:

The US Department of Energy’s exascale computing initiative aims to build supercomputers to solve a wide range of HPC problems, including emerging data science and machine learning problems. The talk will first cover the requirements for exascale computing and highlight various challenges that need to be addressed. The talk will then give an overview of the various technologies that AMD is pursuing to design an Exascale Heterogeneous Processor (EHP), which will serve as the basic building block of an exascale supercomputer. Finally, the talk will conclude by highlighting some of the simulation infrastructure used to evaluate EHP and our effort to open source and share it with the broader research community. Short Bio:

Brad Beckmann has been a member of AMD Research since 2007 and works in Bellevue, WA. Brad completed his PhD degree in the Department of Computer Science at the University of Wisconsin-Madison in 2006 where his doctoral research focused on physical and logical solutions to wire delay in CMP caches. While at AMD Research, he has worked on numerous projects related to memory consistency models, cache coherence, graphics, and on-chip networks. Currently, his primary research focuses on GPU compute solutions and broadening the impact of future AMD Accelerated Processing Unit (APU) servers. Regards, Juan Gómez Luna

Start: 02.03.2018 12:15
Friday March 09, 2018
Start: 09.03.2018 12:15
Wednesday March 14, 2018
Start: 14.03.2018 14:00

 

COMPASS: Computing Platforms Seminar Series

CAB E 72

Speaker: Eric Sedlar, Oracle Labs

 

Title: Why Systems Research Needs Social Science Added to the Computer Science

 

 

 

 

Abstract:

Computer scientists are very good at improving metrics that can be quantified: performance per-core/per-server/per-Watt, scalability, reliability, and are even getting better at a bit fuzzier metrics like accuracy of ML systems. However, it is many of the fuzziest metrics that are driving trends in computing: programmer productivity, usability, cognitive load and/or degree of security provided by a particular system. The biggest trend in computing for the past few decades is the explosion in the use of open-source software in the bulk of computing tasks. This is true even in environments as security-conscious as defense applications, as the stack that needs to execute in an application becomes too complicated for one programmer or one software vendor to comprehend or master. This move to open source software makes most system metrics worse as much of the code run is not optimized for CPU efficiency and may be understood by nobody working for the firm operating the software or its vendors. What is a systems researcher to do in the face of their inconsequential metrics?

Shortbio:

As VP & Technical Director of Oracle Labs, Eric manages a team of close to 200 systems researchers and engineers worldwide. In his tenure in the Labs, Eric has started a number of long-term system research projects that have led to technology transfer into products, including the GraalVM programming language runtime, PGX Parallel Graph Analytics, and the Parfait tool for Program Analysis. His personal research interests have been in the field of data processing and the intersection with compiler technologies. Eric was the co-author of the SIGMOD Best Paper in 2009 and has been an inventor on 85 granted patents.

COMPASS Talks

Friday March 16, 2018
Start: 16.03.2018 12:00
Thursday April 12, 2018
Start: 12.04.2018 11:00

Thursday, 12 April 2018, 11:00-12:00 in CAB E 72

Speaker: Christoph Hagleitner (IBM Research, Rüschlikon)

Title: Heterogeneous Computing Systems for Datacenter and HPC Applications

 

 

 

 

 

Abstract:

For several decades, the technology roadmap has been driven by technology scaling, but it is evident that this will not be sufficient to economically realize large-scale computing applications. Furthermore, the convergence of data-science and HPC leads to significant changes of the workload characteristic of the emerging exascale HPC applications when compared to "classic" HPC applications. Therefore, the innovations that sustain the roadmap towards exascale computing applications come from heterogeneous, dense, workload-optimized systems. In this presentation, I will discuss the current status and show several projects from within IBM Research - Zurich that advance the roadmap towards tomorrows large-scale computing applications.

Short Bio:

Christoph Hagleitner leads the "Heterogeneous Cognitive Computing Systems" group at the IBM Research – Zurich Lab (ZRL) in Ruschlikon, Switzerland. The group focuses on heterogeneous computing systems for cloud datacenters and HPC. Applications include big-data analytics and cognitive computing. He obtained a diploma degree in Electrical Engineering from ETH, Zurich, Switzerland in 1997 and and a Ph.D. degree for a thesis on CMOS-integrated Microsensors from ETH, Zurich, Switzerland in 2002. In 2003 he joined IBM Research to work on the system architecture of a novel probe-storage device (“millipede”-project). In 2008, he started to build up a new research group in the area of accelerator technologies. The team initially focused on on-chip accelerator cores and gradually expanded its research to heterogeneous systems and their applications. 

 

COMPASS Talks

Thursday April 19, 2018
Start: 19.04.2018 11:00

COMPASS: Computing Platforms Seminar Series

CAB E 72

Speaker: Jane Hung (MIT)

Title: The Challenges and Promises of Large-Scale Biological Imaging

 

 

 

 

 

 

Abstract:

Microscopy images contain rich information about the state of cells, tissues, and organisms and are an important part of experiments to address a multitude of basic biological questions and health problems. The Broad Institute of MIT and Harvard’s Imaging Platform works with dozens of collaborators around the world to design and execute large-scale microscopy-based experiments in order to identify the causes and potential cures of disease. These experiments, though carried out in a non-profit environment, have led to the discovery of drugs effective in animal models of disease, and the uncovering of mechanisms underlying other diseases and biological processes.

Most recently, we have been working on software to support the increased physiological complexity of modern screening systems, for example, using whole organisms and co-cultured cell types. As well, our machine learning tools allow a biologists’ intuition to guide the computer to measure subtle phenotypes. We are also working to use patterns of morphological features to group samples by similarity, in order to identify drug targets and gene function. Ultimately, we aim to make microscopy images as computable as other sources of genomic and chemical information.

Short Bio:

Jane received her Ph.D. in the Department of Chemical Engineering at MIT and is interested in how accessible software can make processes more efficient. She had her first computer vision experience at an internship at Novartis in Basel working on automated drug manufacturing monitoring. From there, she joined Anne Carpenter's biological imaging analysis lab at the Broad Institute. She has worked on machine learning-based software application CellProfiler Analyst in collaboration with David Dao as well as deep learning-based object detection software Keras R-CNN in collaboration with Allen Goodman.

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COMPASS Talks

Thursday April 26, 2018
Start: 26.04.2018 11:00

 

COMPASS: Computing Platforms Seminar Series

CAB E 72

 

Thursday, 26 April 2018, 11:00-12:00 in CAB E 72

Speaker: Spyros Blanas (Ohio State University, USA)

Title: Scaling database systems to high-performance  computers

 

 

 

 

 

Abstract:

Processing massive datasets quickly requires warehouse-scale computers. Furthermore, many massive datasets are multi-dimensional arrays which are stored in formats like HDF5 and NetCDF that cannot be directly queried using SQL. Parallel array database systems like SciDB cannot scale in this environment that offers fast networking but very limited I/O bandwidth to shared, cold storage: merely loading multi-TB array datasets in SciDB would take days--an unacceptably long time for many applications.

In this talk, we will present ArrayBridge, a common interoperability layer for array file formats. ArrayBridge allows scientists to use SciDB, TensorFlow and HDF5-based code in the same file-centric analysis pipeline without converting between file formats. Under the hood, ArrayBridge manages I/O to leverage the massive concurrency of warehouse-scale parallel file systems without modifying the HDF5 API and breaking backwards compatibility with legacy applications. Once the data has been loaded in memory, the bottleneck in many array-centric queries becomes the speed of data repartitioning between different nodes. We will present an RDMA-aware data shuffling abstraction that directly converses with the network adapter in InfiniBand verbs and can repartition data up to 4X faster than MPI. We conclude by highlighting research opportunities that need to be overcome for data processing to scale to warehouse-scale computers.

Short Bio: 

Spyros Blanas is an assistant professor in the Department of Computer Science and Engineering at The Ohio State University. His research interest is high-performance database systems, and his current goal is to build a database system for high-end computing facilities. He has received the IEEE TCDE Rising Star Award and a Google Research Faculty award. He received his Ph.D. at the University of Wisconsin–Madison and part of his Ph.D. dissertation was commercialized in Microsoft's flagship data management product, SQL Server, as the Hekaton in-memory transaction processing engine.

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COMPASS Talks

Monday April 30, 2018
Start: 30.04.2018 16:15

Date: 30 April 2018

Time: 16:15 - 17:15

Place: ETH Zurich, main campus CAB G 61

Speaker: Prof. Wen-Mei Hwu, University of Illinois at Urbana-Champaign

Host: Prof. Onur Mutlu

ABSTRACT:

We have been experiencing two very important developments in computing. On the one hand, a tremendous amount of resources have been invested into innovative applications such as first-principle based models, deep learning and cognitive computing. On the other hand, the industry has been taking a technological path where traditional scaling is coming to an end and application performance and power efficiency vary by more than two orders of magnitude depending on their parallelism, heterogeneity, and locality. A “perfect storm” is beginning to form from the fact that data movement has become the dominating factor for both power and performance of high-valued applications. It will be critical to match the compute throughput to the data access bandwidth and to locate the compute at where the data is. Much has been and continuously needs to be learned about of algorithms, languages, compilers and hardware architecture in this movement. What are the killer applications that may become the new diver for future technology development? How hard is it to program existing systems to address the date movement issues today? How will we program future systems? How will innovations in memory devices present further opportunities and challenges in designing new systems? What is the impact on long-term software engineering cost on applications (and legacy applications in particular)? In this talk, I will present some lessons learned as we design the IBM-Illinois C3SR Erudite system inside this perfect storm.

 

BIOGRAPHY:

Wen-mei W. Hwu is a Professor and holds the Sanders-AMD Endowed Chair in the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign. He is also Chief Scientist of UIUC Parallel Computing Institute and director of the IMPACT research group (www.crhc.uiuc.edu/Impact). He co-directs the IBM-Illinois Center for Cognitive Computing Systems Research (C3SR) and serves as one of the principal investigators of the NSF Blue Waters Petascale supercomputer. For his contributions, he received the ACM SigArch Maurice Wilkes Award, the ACM Grace Murray Hopper Award, the IEEE Computer Society Charles Babbage Award, the ISCA Influential Paper Award, the IEEE Computer Society B. R. Rau Award and the Distinguished Alumni Award in Computer Science of the University of California, Berkeley. He is a fellow of IEEE and ACM. Dr. Hwu received his Ph.D. degree in Computer Science from the University of California, Berkeley.

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 D-INFK Distinguished Colloquium

Wednesday May 09, 2018
Start: 09.05.2018 14:00

 

COMPASS: Computing Platforms Seminar Series

CAB E 72

Speaker: Bastian Hossbach (Oracle Labs)

 

Title: Modern programming languages and code generation in the Oracle Database

 

 

 

 

Abstract:

In this talk, we will present the Oracle Database Multilingual Engine (MLE). MLE is an experimental feature for the Oracle Database that enables developers to write stored procedures and user-defined functions in modern programming languages such as JavaScript and Python. Special attention was payed to embrace the rich ecosystems of tools and libraries developed for those languages in order to make the developer's experience as familiar as possible. We will show several demos of MLE in action and discuss the challenges of integrating a language runtime with a database system. Under the hood, MLE is powered by the speculative JIT compiler Graal. Having a modern JIT compiler inside a database system not only allows for efficiently running user-defined code, but also for runtime compilation and specialization of SQL expressions and other parts of a query plan to speed up overall query execution.

Short Bio:

Since 2015, Bastian is a researcher at Oracle Labs in Zurich, Switzerland. He is currently working on a high-performance query execution engine for database management systems that is capable of executing query plans combined with user-defined scripts written in a variety of languages (e.g., JavaScript, Python). Bastian received a PhD degree in computer science from the University of Marburg, Germany, in 2015. Prior to Oracle Labs, he has been involved in several projects in the areas of data analytics, data processing and IT security.

COMPASS Talks

Wednesday May 16, 2018
Start: 16.05.2018 11:00

Wednesday, 16 May 2018, 11:00-12:00 in CAB E 72

Speaker: Carsten Binnig (TU Darmstadt)

Title: Towards Interactive Data Exploration

 

 

 

Abstract:

Technology has been the key enabler of the current Big Data movement. Without open-source tools like R and Hadoop, as well as the advent of cheap, abundant computing and storage in the cloud, the ongoing trend toward datafication of almost every research field and industry could never have occurred. However, the current Big Data tool set is ill-suited for interactive data exploration of new data making the knowledge discovery process a major bottleneck in our data-driven society.

In this talk, I will first give an overview of challenges for interactive data exploration on large data sets and then present current research results that revisit the design of existing data management systems, from the query interface over the execution models to the storage and the underlying hardware to enable interactive data exploration.

Short Bio:

Carsten Binnig is a Full Professor in the Computer Science department at TU Darmstadt and an Adjunct Associate Professor in the Computer Science department at Brown University. Carsten received his PhD at the University of Heidelberg in 2008. Afterwards, he spent time as a postdoctoral researcher in the Systems Group at ETH Zurich and at SAP working on in-memory databases. Currently, his research focus is on the design of data management systems for modern hardware as well as modern workloads such as interactive data exploration and machine learning. He has recently been awarded a Google Faculty Award and a VLDB Best Demo Award for his research.

COMPASS Talks

Friday May 18, 2018
Start: 18.05.2018 10:00

CAB E 72

Rodrigo Bruno (INESC-ID Lisboa): "Taming Long Tail Latencies with Allocation Context aware Pretenuring"

Abstract:

Latency sensitive services such as credit-card fraud detection and website targeted advertisement rely on Big Data platforms which run on top of memory managed runtimes, such as the Java Virtual Machine. These platforms, however, suffer from unpredictable and unacceptably high pause times due to inadequate memory management decisions This problem has been previously identified, and results show that current memory management techniques are ill-suited for applications that hold in memory massive amounts of long-lived objects (which is the case for a wide spectrum of Big Data applications). Previous works reduce such application pauses by allocating objects in off-heap, in special allocation regions/generations, or by using ultra-low latency Garbage Collectors (GC). However, all these solutions either require a combination of programmer effort and knowledge, source code access or off-line profiling, or impose a significant impact on application throughput in order to reduce application pauses (which is the case of ultra-low collectors). To solve this problem, we propose ROLP, a runtime object lifetime profiler that profiles application code at runtime. ROLP is targeted to help pretenuring GC algorithms deciding where to allocate an object in order to reduce overall fragmentation and GC effort, thus reducing application pauses. ROLP is implemented for the OpenJDK 8 and was evaluated with a recently proposed pretenuring collector (NG2C). Results show long tail latencies reductions of up to 51% for Lucene (search engine), 85% for GraphChi (graph engine), and 69% for Cassandra (key-value store). This is achieved with negligible throughput (< 6%) and memory overhead, and with zero programmer effort and no source code access.

Short Bio:

Rodrigo Bruno received his BSc (2012) and MSc (2014) degrees in Information Systems and Computer Engineering from Instituto Superior Técnico (IST), University of Lisbon, where he is now pursuing a PhD degree. At the same time, Rodrigo is a researcher at the Distributed Systems Group in INESC-ID Lisboa, and a teaching assistant at IST. His research is mostly focused on Garbage Collection algorithms for large scale latency sensitive applications. In the course of the last years, Rodrigo has collaborated and interned with several companies (such as Microsoft Research and Google) and also contributed to several opensource projects. ;

Thursday May 24, 2018
Start: 24.05.2018 11:00

 

COMPASS: Computing Platforms Seminar Series

CAB E 72

 

Speaker: Cagri Balkesen (Oracle Labs)

Title: RAPID: In-Memory Analytical Query Processing Engine with Extreme Performance per Watt

 

 

 

 

Abstract:

Today, an ever increasing amount of transistors are packed into processor designs with extra features to support a broad range of  applications. As a consequence, processors are becoming more and more complex and power hungry. At the same time, they only sustain an  average performance for a wide variety of applications while not providing the best performance for specific applications. In this paper, we demonstrate through a carefully designed modern data processing system called RAPID and a simple, low-power processor  specially tailored for data processing that at least an order of  magnitude performance/power improvement in SQL processing can be achieved over a modern system running on today's complex processors.  RAPID is designed from the ground up with hardware/ software co-design  in mind to provide architecture-conscious extreme performance while  consuming less power in comparison to the modern database systems. The  paper presents in detail the design and implementation of RAPID, a relational, columnar, in-memory query processing engine supporting analytical query workloads.

Short bio: 

Cagri completed his PhD in 2014 in the Systems Group at ETH Zurich supervised by Prof. Gustavo Alonso. His broader research interests are data processing on modern computing architectures as well as data stream processing. He holds a MSc in Computer Science of ETH Zurich and a BSc in Computer Engineering of the Middle East Technical University (METU) in Turkey. His PhD thesis at ETH Zurich addresses the design and implementation of in-memory joins on modern hardware architectures with massive multi-core parallelism and the paradigm shift towards in-memory processing. His work on main-memory hash joins received the Best-Paper Runner-Up award at IEEE ICDE 2013. Cagri was a recipient of Excellence Scholarship from ETH Zurich and he holds several US-patents based on his work at IBM and Oracle Labs.

COMPASS Talks

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Friday June 15, 2018
Start: 15.06.2018 11:00

COMPASS: Computing Platforms Seminar Series

CAB E 72 


Friday, 15 Juni 2018, 11:00-12:00 in CAB E 72

Speaker: Nitin Agrawal (Samsung Research)

Title: Low-Latency Analytics on Colossal Data Streams with SummaryStore

 

  

Abstract:

Data empowers learning; but soon, we may have too much of it, from sensors, machines, and personal devices, to store and analyze in a timely and cost-effective manner. In this talk I will present SummaryStore, an approximate storage system designed to support analytical and machine learning workloads such as forecasting, anomaly detection, and traffic monitoring, on large volumes of time-series data (∼petabyte per node). SummaryStore contributes time-decayed summaries, a novel abstraction for aggressively summarizing data streams while preserving accuracy. I'll also briefly discuss other research opportunities in this area and future work. This work was presented at SOSP '17; more details are available at http://pages.cs.wisc.edu/~nitina/summarystore/

Short Bio: 

Nitin Agrawal heads the systems research lab at Samsung’s Artificial Intelligence Center in Mountain View, CA. His research lies broadly in systems, with an emphasis on storage, mobile, and distributed systems, and has received multiple best–paper awards, led to commercial & academic impact, an outstanding patent award, and widespread media attention. He served as the program committee chair for USENIX FAST ’18 and earned his doctorate from the University of Wisconsin-Madison in 2009.


COMPASS Talks

Friday June 22, 2018
Start: 22.06.2018 10:00

CAB E 72

Talk by Ana Klimovic (Stanford University): Elastic Ephemeral Storage for Serverless Computing

Abstract:

Serverless computing is an increasingly popular cloud service, enabling users to launch thousands of short-lived tasks ("lambdas") with high elasticity and fine-grain resource billing. High elasticity and granular resource allocation make serverless computing appealing for interactive data analytics. However, a key challenge is sharing intermediate data between tasks in analytics jobs. Exchanging data directly between short-lived lambdas is difficult, thus the natural approach is to store ephemeral data in a common remote data store. Unfortunately, existing storage systems are not designed to meet the elasticity, performance and granular cost requirements of serverless applications. We first characterize the ephemeral I/O requirements of serverless analytics applications. We then present our design and implementation of a distributed data store that elastically and automatically scales to rightsize storage cluster resources across multiple dimensions (storage capacity, CPU cores and network bandwidth). We show the system cost-effectively satisfies dynamic application I/O requirements. Short

Bio:

Ana Klimovic is a final year Ph.D. student at Stanford University, advised by Professor Christos Kozyrakis. Her research interests are in computer systems and architecture. She is particularly interested in building high performance, resource efficient storage and computing systems for large-scale datacenters. Ana has interned at Facebook and Microsoft Research. Before coming to Stanford, Ana graduated from the Engineering Science undergraduate program at the University of Toronto. She is a Microsoft Research Ph.D. Fellow, Stanford Graduate Fellow and Accel Innovation Scholar. --

Friday July 06, 2018
Start: 06.07.2018 15:00

COMPASS: Computing Platforms Seminar Series

CAB E 72 

Friday, 6 July 2018, 15:00-16:00

Speaker: Martin Burtscher (Texas State University) 

Title: Automatic Hierarchical Parallelization of Linear Recurrences

 

 

 

Abstract:

Many important computations from various fields are instances of linear recurrences. Prominent examples include prefix sums in parallel processing and recursive filters in digital signal processing. Later result values depend on earlier result values in recurrences, making it a challenge to compute them in parallel. We present a brand-new work-, space-, and communication-efficient algorithm to compute linear recurrences that is based on Fibonacci numbers, amenable to automatic parallelization, and suitable for GPUs. We implemented our approach in a small compiler that translates recurrences expressed in signature notation into CUDA code. Moreover, we discuss the domain-specific optimizations performed by our compiler to produce state-of-the-art implementations of linear recurrences. Compared to the fastest prior GPU codes, all of which only support certain types of recurrences, our automatically parallelized code performs on par or better in most cases. In fact, for standard prefix sums and single-stage IIR filters, it reaches the throughput of memory copy for large inputs, which cannot be surpassed. On higher-order prefix sums, it performs nearly as well as the fastest handwritten code. On tuple-based prefix sums and 1D recursive filters, it outperforms the fastest preexisting implementations.

Shirt Bio:

Martin Burtscher is a Professor in the Department of Computer Science at Texas State University. He received the BS/MS degree from ETH Zurich and the PhD degree from the University of Colorado at Boulder. Martin's current research focuses on parallelization of complex programs for GPUs as well as on automatic synthesis of data-compression algorithms. He has co-authored over 100 peer-reviewed scientific publications. Martin is a distinguished member of the ACM and a senior member of the IEEE.


 

Tuesday July 10, 2018
Start: 10.07.2018 14:30

HG D 22

Simon Gerber, PhD Defense

Title: Authorization, Protection, and Allocation of Memory in a Large System