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Friday December 08, 2017
Start: 08.12.2017 12:15

CAB G 61

Kaveh Razavi (Vrije Universiteit Amsterdam)

Title: The Sad State of Software on Unreliable and Leaky Hardware


Hardware that we use today is unreliable and leaky. Bit flips plague a substantial part of the memory hardware that we use today and there are a variety of side channels that leak sensitive information about the system. In this talk, I will briefly talk about how we turned Rowhammer bit flips into practical exploitation vectors compromising browsers, clouds and mobile phones. I will then talk about a new side-channel attack that uses the traces that the memory management unit of the processor leaves in its data/instruction caches to derandomize secret pointers from JavaScript. This attack is very powerful: it breaks address-space layout randomization (ASLR) in the browser on all the 22 modern CPU architectures that we tried in only tens of seconds and it is not easy to fix. It is time to rethink our reliance on ASLR as a basic security mechanism in sandboxed environments such as JavaScript.


Kaveh Razavi is starting as an assistant professor in the VUSec group of Vrije Universiteit Amsterdam next year. Besides building systems, he is currently mostly interested in the security implications of unreliable and leaky general-purpose hardware. He regularly publishes at top systems and systems security venues and his research has won multiple industry and academic awards including different Pwnies and the CSAW applied best research paper. In the past, he has built network and storage stacks for rack-scale computers at Microsoft Research (2014-2015), worked on the scalability issues of cloud virtual machines for his PhD (2012-2015) and hacked on Barrelfish as a master student (2010-2011)!

Monday December 11, 2017
Start: 11.12.2017 16:15

CAB G 61 

Distinguished Computer Science Colloquium:

Subhasish Mitra, Stanford University, California, USA

Transforming Nanodevices into Nanosystems: The N3XT 1,000X

Host: Prof. Onur Mutlu


Coming generations of information technology will process unprecedented amounts of loosely-structured data, including streaming video and audio, natural languages, real-time sensor readings, contextual environments, or even brain signals. The computation demands of these abundant-data applications (e.g., deep learning) far exceed the capabilities of today’s computing systems, and cannot be met by isolated improvements in transistor technologies, memories, or integrated circuit (IC) architectures alone. Transformative nanosystems, which leverage the unique properties of emerging nanotechnologies to create new IC architectures, are required to deliver unprecedented functionality, performance and energy efficiency. However, emerging nanomaterials and nanodevices face major obstacles such as inherent imperfections and variations. Thus, realizing working circuits, let alone transformative nanosystems, has been infeasible. The N3XT (Nano-Engineered Computing Systems Technology) approach overcomes these challenges through recent innovations across the computing stack: (a) new logic devices using nanomaterials such as one-dimensional carbon nanotubes (and two-dimensional semiconductors) for high performance and energy efficiency; (b) high-density non-volatile resistive and magnetic memories; (c) ultra-dense (e.g., monolithic) three-dimensional integration of thin layers of logic and memory with fine-grained connectivity; (d) new IC architectures for computation immersed in memory; and, (e) new materials technologies and their integration for efficient heat removal. N3XT hardware prototypes represent leading examples of transforming the basic science of nanomaterials and nanodevices into actual nanosystems. Compared to conventional (2D) systems, N3XT architectures promise to improve the energy efficiency of abundant-data applications significantly, in the range of three orders of magnitude. Such massive benefits enable new frontiers of applications for a wide range of computing systems, from embedded systems to the cloud.


Subhasish Mitra is Professor of Electrical Engineering and of Computer Science at Stanford University, where he directs the Stanford Robust Systems Group and co-leads the Computation focus area of the Stanford SystemX Alliance. He is also a faculty member of the Stanford Neurosciences Institute. Before joining the Stanford faculty, he was a Principal Engineer at Intel Corporation. Prof. Mitra's research interests range broadly across robust computing, nanosystems, VLSI design, CAD, validation and test, and neurosciences. He, jointly with his students and collaborators, demonstrated the first carbon nanotube computer and the first 3D Nanosystem with computation immersed in memory. These demonstrations received wide-spread recognitions (cover of NATURE, research highlight to the United States Congress by the National Science Foundation, highlight as "important, scientific breakthrough" by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Public Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post and numerous others worldwide). His earlier work on X-Compact test compression has been key to cost-effective manufacturing and high-quality testing of a vast majority of electronic systems. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools. Prof. Mitra's honors include the ACM SIGDA/IEEE CEDA Richard Newton Technical Impact Award in Electronic Design Automation (a test of time honor), the Semiconductor Research Corporation's Technical Excellence Award, the Intel Achievement Award (Intel’s highest corporate honor), and the Presidential Early Career Award for Scientists and Engineers from the White House (the highest United States honor for early-career outstanding scientists and engineers). He and his students published several award-winning papers at major venues: IEEE/ACM Design Automation Conference, IEEE International Solid-State Circuits Conference, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, and the Symposium on VLSI Technology. At Stanford, he has been honored several times by graduating seniors "for being important to them during their time at Stanford." Prof. Mitra served on the Defense Advanced Research Projects Agency's (DARPA) Information Science and Technology Board as an invited member. He is a Fellow of the ACM and the IEEE.

Friday December 15, 2017
Start: 15.12.2017 12:00

CAB E 72

Kevin Chang (Carnegie Mellon University)

Title: Understanding and Improving the Latency of DRAM-Based Memory Systems


Over the past two decades, the storage capacity and access bandwidth of main memory have improved tremendously, by 128x and 20x, respectively. These improvements are mainly due to the continuous technology scaling of DRAM (dynamic random-access memory), which has been used as the physical substrate for main memory. In stark contrast with capacity and bandwidth, DRAM latency has remained almost constant, reducing by only 1.3x in the same time frame. Therefore, long DRAM latency continues to be a critical performance bottleneck in modern systems. Increasing core counts, and the emergence of increasingly more data-intensive and latency-critical applications further stress the importance of providing low-latency memory accesses. In this talk, we will identify three main problems that contribute significantly to long latency of DRAM accesses. To address these problems, we show that (1) augmenting DRAM chip architecture with simple and low-cost features, and (2) developing a better understanding of manufactured DRAM chips together leads to significant memory latency reduction. Our new proposals significantly improve both system performance and energy efficiency.


Kevin Chang is a recent Ph.D. graduate in electrical and computer engineering from Carnegie Mellon University, where he's advised by Prof. Onur Mutlu. He is broadly interested in computer architecture, large-scale systems, and emerging technologies. Specifically, his graduate research focuses on improving performance and energy-efficiency of memory systems. He will join Facebook as a research scientist. He was a recipient of the SRC and Intel fellowship.

Thursday December 21, 2017
Start: 21.12.2017 17:00

Title: Building Distributed Storage with Specialized Hardware


  • Gustavo Alonso
  • Timothy Roscoe
  • Torsten Hoefler
  • Ken Eguro (MSR Redmond, USA)  

Room: HG D 22