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Thursday November 21, 2019
Start: 21.11.2019 10:00

Thursday, 21. November 2019, 10:00-11:00 in CAB E 72

Speaker: Tamás Hauer, Technical Program Manager, SRE, Google Zurich

Title: Meaningful Availability


High availability is a critical requirement for cloud applications; having a metric that meaningfully captures it is useful for users and system developers. Commonly used benchmarks are either too complex to be actionable or fail to capture the true perception of users, which leads to miscommunication, and suboptimal engineering decisions. We propose two improvements to availability measurements. A novel metric, "user-uptime" directly models user-perceived availability and avoids the bias often found in alternatives. A presentation paradigm "windowed availability" supports a holistic view by integrating timescales from per-minute to monthly granularity and allows to distinguish between many short periods of unavailability or fewer longer ones. We demonstrate the benefits of windowed user-uptime on synthetic models and on production data from Google's G Suite. Today, all G Suite products are instrumented with this novel metric, it is used both to support engineering decisions and to communicate system health to enterprise customers.


Tamás Hauer holds a PhD in theoretical physics. After a brief career as a physicist at the Max-Planck-Institut and CERN, he worked as a research associate at the department of Applied Computer Science of the University of West of England, leading a group in the area of semantic web, grid services and health informatics. He was work package leader of the European FP5 Mammogrid and FP6 Health-e-Child projects. As the CTO of the Swiss startup Prodema Medical / McMRI, he led the development of appMRI, a brain MRI image analysis platform to launch and certification as a class IIa medical device. He joined Site Reliability Engineering of Google Zürich in 2016 as a Technical Program Manager, his current interest is data analysis of service level indicators and service level objectives.



Thursday November 28, 2019
Start: 28.11.2019 10:00

Thursday, 28. November 2019, 10:00-11:00 in CAB E 72

Speaker: Djordje Zegarac and Martin Marciniszyn (Tensor Technologies)

Title: High Frequency Trading and FPGAs 


High-Frequency Trading (HFT) platforms were typically implemented in software on traditional CPUs with high performance network adapters. However, the industry-wide race to "Zero Latency" has led the trading world to explore alternative system architectures that would minimize the internal latency. Field-Programmable Gate Arrays (FPGAs) offer the superior performance with deterministic execution while providing custom implementation flexibility. Due to these valuable architectural properties FPGAs became the integral part of HFT industry in accelerating trading solutions and reducing wire to wire latencies. In this talk we are going to outline the general architecture of our system and describe the main design challenges.


Djordje Zegarac received the B.Sc. degree in Electrical Engineering from the University of Calgary, Canada in 2011, the M.Sc. degree in Electronics and Microelectronics from Ecole Polytechnique Fédérale de Lausanne and IBM Research, Switzerland in 2014. He worked as an IC Digital Design Engineer at u-blox, and as FPGA SoC Development Engineer at Enclustra, Switzerland. Currently, he is employed by Tensor Technologies as an FPGA Engineer. His main research interest is in the area of ASIC/FPGA design and hardware acceleration.

Martin Marciniszyn received a Ph.D. in Computer Science from ETH Zurich in 2007. Afterwards he spent the largest part of his professional career as a quant researcher at IMC Trading, one of the largest global HFT companies. Currently, he is the CTO of Tensor Technologies.


Tuesday December 17, 2019
Sunday January 19, 2020
Monday January 20, 2020
Tuesday January 21, 2020
Wednesday January 22, 2020
Start: 19.01.2020
End: 22.01.2020
Monday February 03, 2020
Start: 03.02.2020 10:00
End: 03.02.2020 11:00

Monday, 3 February 2020, 10:00-11:00 in CAB E 72

Speaker: Lars Eggert, NetAppZurich

Title: QUIC – Will it Replace TCP/IP?


QUIC is a new UDP-based transport protocol for the Internet, and specifically, the web. Originally designed and deployed by Google, it already makes up 35% of Google's egress traffic, which corresponds to about 7% of all Internet traffic. The strong interest by many other large Internet players in the ongoing IETF standardization of QUIC is likely to lead to an even greater deployment in the near future.

This talk will highlight:

  • Unique design aspects of QUIC
  • Differences to the conventional HTTP/TLS/TCP web stack
  • Early performance numbers
  • Potential side effects of a broader deployment of QUIC


Lars Eggert is Technical Director for Networking in NetApp's Office of the CTO based near Helsinki, Finland. He is an experienced technologist with deep expertise in network architectures, systems and protocol design, ranging from the Internet to datacenter to IoT/edge environments.

Lars has been leading networking standardization as part of the IETF steering group and architecture board for two decades and has chaired its research arm, the IRTF. He currently chairs the QUIC working group that is delivering a major new Internet protocol, and he serves on the program and organization committees of academic conferences such as ACM SIGCOMM, as well as numerous other boards.

Lars received his Ph.D. in Computer Science from the University of Southern California (USC) in 2003. Before joining NetApp in 2011, he was a Principal Scientist at Nokia and served on the corporation’s CTO and CEO Technology Councils of senior technology experts. In parallel, from 2009-2014, Lars was an Adjunct Professor at Aalto University, Finland’s top technical university. From 2003-2006, he was a senior researcher at NEC Labs.



Wednesday February 05, 2020
Start: 05.02.2020 10:00

05.02.2020 10:00 (HG D22)

PhD Defense: Kaan Kara

Title: Specialized Hardware Solutions for In-Database Analytics and Machine Learning 

Committee: Gustavo Alonso (ETH), Ce Zhang (ETH), Onur Mutlu (ETH), and Christoph Hagleitner (IBM Research Zurich).


Friday February 07, 2020
Start: 07.02.2020 14:00

07.02.2020 Room: TBA

PhD Defense: Reto Achermann

Title: On Memory Addressing

Committee: Timothy Roscoe (ETH Zurich) David Basin (ETH Zurich) Gernot Heiser (UNSW and Data61) David Cock (ETH Zurich)


Tuesday February 11, 2020
Start: 11.02.2020 16:00

HG D 22

Zaheer Chothia- PhD Defense

Title: TBA