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Thursday November 28, 2019
Start: 28.11.2019 10:00

Thursday, 28. November 2019, 10:00-11:00 in CAB E 72

Speaker: Djordje Zegarac and Martin Marciniszyn (Tensor Technologies)

Title: High Frequency Trading and FPGAs 

Abstract:

High-Frequency Trading (HFT) platforms were typically implemented in software on traditional CPUs with high performance network adapters. However, the industry-wide race to "Zero Latency" has led the trading world to explore alternative system architectures that would minimize the internal latency. Field-Programmable Gate Arrays (FPGAs) offer the superior performance with deterministic execution while providing custom implementation flexibility. Due to these valuable architectural properties FPGAs became the integral part of HFT industry in accelerating trading solutions and reducing wire to wire latencies. In this talk we are going to outline the general architecture of our system and describe the main design challenges.

Bio:

Djordje Zegarac received the B.Sc. degree in Electrical Engineering from the University of Calgary, Canada in 2011, the M.Sc. degree in Electronics and Microelectronics from Ecole Polytechnique Fédérale de Lausanne and IBM Research, Switzerland in 2014. He worked as an IC Digital Design Engineer at u-blox, and as FPGA SoC Development Engineer at Enclustra, Switzerland. Currently, he is employed by Tensor Technologies as an FPGA Engineer. His main research interest is in the area of ASIC/FPGA design and hardware acceleration.

Martin Marciniszyn received a Ph.D. in Computer Science from ETH Zurich in 2007. Afterwards he spent the largest part of his professional career as a quant researcher at IMC Trading, one of the largest global HFT companies. Currently, he is the CTO of Tensor Technologies.


 COMPASS TALKS 

Tuesday December 17, 2019
Sunday January 19, 2020
Monday January 20, 2020
Tuesday January 21, 2020
Wednesday January 22, 2020
Start: 19.01.2020
End: 22.01.2020
Monday February 03, 2020
Start: 03.02.2020 10:00
End: 03.02.2020 11:00

 

A special feature for this talk is an industry panel following it, including guests from top companies in the Web sector — Mozilla, Cloudflare, and Fastly (details below).

 

Monday, 3 February 2020, 10:00-11:00 (The panel will finish at the lates at 11:30) in CAB G 51

Speaker: Lars Eggert, NetAppZurich

Title: QUIC – Will it Replace TCP/IP?

 

 

Panelists:

• Martin Thomson (Mozilla)

• Lucas Pardue (Cloudflare)

• Jana Iyengar (Fastly)

• Lars Eggert (NetApp)

 

Abstract:

QUIC is a new UDP-based transport protocol for the Internet, and specifically, the web. Originally designed and deployed by Google, it already makes up 35% of Google's egress traffic, which corresponds to about 7% of all Internet traffic. The strong interest by many other large Internet players in the ongoing IETF standardization of QUIC is likely to lead to an even greater deployment in the near future.

This talk will highlight:

  • Unique design aspects of QUIC
  • Differences to the conventional HTTP/TLS/TCP web stack
  • Early performance numbers
  • Potential side effects of a broader deployment of QUIC

 

Bio:

Lars Eggert is Technical Director for Networking in NetApp's Office of the CTO based near Helsinki, Finland. He is an experienced technologist with deep expertise in network architectures, systems and protocol design, ranging from the Internet to datacenter to IoT/edge environments.

Lars has been leading networking standardization as part of the IETF steering group and architecture board for two decades and has chaired its research arm, the IRTF. He currently chairs the QUIC working group that is delivering a major new Internet protocol, and he serves on the program and organization committees of academic conferences such as ACM SIGCOMM, as well as numerous other boards.

Lars received his Ph.D. in Computer Science from the University of Southern California (USC) in 2003. Before joining NetApp in 2011, he was a Principal Scientist at Nokia and served on the corporation’s CTO and CEO Technology Councils of senior technology experts. In parallel, from 2009-2014, Lars was an Adjunct Professor at Aalto University, Finland’s top technical university. From 2003-2006, he was a senior researcher at NEC Labs.

 ---  

COMPASS TALKS 

Wednesday February 05, 2020
Start: 05.02.2020 10:00

05.02.2020 10:00 (HG D22)

PhD Defense: Kaan Kara

Title: Specialized Hardware Solutions for In-Database Analytics and Machine Learning 

Committee: Gustavo Alonso (ETH), Ce Zhang (ETH), Onur Mutlu (ETH), and Christoph Hagleitner (IBM Research Zurich).

 

Friday February 07, 2020
Start: 07.02.2020 14:00

07.02.2020  14:00

Room: HG F 26.3

PhD Defense: Reto Achermann

Title: On Memory Addressing

Committee: Timothy Roscoe (ETH Zurich) David Basin (ETH Zurich) Gernot Heiser (UNSW and Data61) David Cock (ETH Zurich)

 

Tuesday February 11, 2020
Start: 11.02.2020 16:00

HG D 22

Zaheer Chothia- PhD Defense

Title: Explaining, Measuring and Predicting Effects in Layered Systems

Committee:

• Prof. Dr. Timothy Roscoe

• Prof. Dr. Gustavo Alonso

• Prof. Dr. Rodrigo Fonseca (Brown University)

Thursday February 27, 2020
Start: 27.02.2020 10:00

Thursday27 February 2020, 10:00-11:00  CAB E 72

Speaker: Alberto Lerner (University of Fribourg)

Title: Rethinking the Interactions between In-Memory Databases and Storage

 

 

 

 

 

Abstract:

In-memory databases rely on non-volatile storage devices for services such as durability and recovery. SSDs can provide the high-performance these services require. However, there are at least two problems with the way these systems currently interact. First, when performance problems occur, SSDs offer no mechanism to help analyze them. The only alternative is to instrument the database side of the problem and conjecture about what might be the cause of performance degradation. The second problem is that adequately scheduling an in-memory database workload can benefit from having storage and database exchange signals, which is not feasible using the currently accepted separation of concerns between these systems.

In this talk, we present how we are designing solutions for both problems with the help of an open-source firmware SSD device. The device allows us to change and add to the existing logic that an SSD implements internally. We also discuss how some specific changes in the architecture of SSDs could greatly benefit in-memory database workloads. We believe that SSDs with such flexibility are an essential tool towards co-designing a new class of high-performance storage/database stack.

Bio:

Alberto Lerner is a Senior Researcher at the eXascale Infolab at the University of Fribourg, Switzerland. His interests include systems that explore closely coupling of hardware and software in order to realize untapped performance and/or functionality. Previously, he spent years in the industry consulting for large, data-hungry verticals such as finance and advertisement. He had also been part of the teams behind a few different database engines: IBM's DB2, working on robustness aspects of the query optimizer, Google's Bigtable, on elasticity aspects, and MongoDB, on general architecture. Alberto received his Ph.D. from ENST - Paris (now ParisTech), having done his thesis research work at INRIA/Rocquencourt and NYU. He's also done post-doctoral work at IBM Research (both at T.J. Watson and Almaden).

Tuesday March 24, 2020
Start: 24.03.2020

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Wednesday March 25, 2020

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Monday April 27, 2020

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Friday May 01, 2020

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Thursday July 30, 2020
Start: 24.03.2020
End: 30.07.2020

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