Talk by Anup Kumar Das (IMEC Netherlands): System Design Challenges: From Von-Neumann to Emerging Neuromorphic Architectures
As the performance demands of applications are growing, multiple processing cores are integrated together to form multiprocessor systems. Energy minimization is a primary optimization objective for these systems. An emerging concern for designs at deep-submicron technology nodes (65nm and below) is the lifetime reliability, as escalating power density and hence temperature variation continues to accelerate wear-out leading to a growing prominence of device defects. As such, reliability and energy need to be incorporated in the multiprocessor design methodology, addressing two key aspects: • lifetime amelioration, i.e. improving the lifetime reliability through energy- and performance-aware intelligent task/thread mapping; and • graceful degradation, i.e. determining the task/thread mapping for different fault-scenarios while minimizing the energy consumption and providing a graceful performance degradation. On the other hand, neuromorphic computing, from its inception has been driven by a vision of emulating the computing power of the brain, both in capacity and architecture/performance. However, it is yet to be accepted as an economically productive technology and widely used by researchers outside its core practitioners. Over the last few years, there has been a regained interest by several research groups and corporate R&D, not traditionally linked to this domain [TrueNorth, Spinnaker]. One major reason for this is the advent of new devices (e.g., non-volatile memories) that could integrate many more synapses within a given silicon area. Considering the high level of maturity of standard Von-Neumann architectures and the relentless research progress in neuromorphic computing, future computing systems are expected to integrate these two computing paradigms. This talk will address system design challenges starting with Von-Neumann architectures and how these challenges transformed to emerging heterogeneous systems incorporating neuromorphic computing.
Dr. Anup Das received the B.Eng. degree in Electronics and Telecommunication Engineering from Jadavpur University, India, in 2004. From 2004 to 2007 he was with STMicroelectronics Ltd as an IC design engineer. From 2007 to 2011 he was with LSI Corporation (formerly Agere Systems) as design-for-test engineer for storage SoCs. He received the Ph.D. degree in computer engineering in the area of embedded systems from the National University of Singapore, in 2014. From 2014 to 2015 he was a post-doctoral research fellow at the University of Southampton developing machine learning based run-time systems. Over these years, his research interests included reliability and energy-aware system architecture, application mapping and scheduling on multiprocessor platforms and resource management for multimedia multiprocessor systems. He is currently working at IMEC, one the leading microelectronics centers in Europe, leading the development of run-time systems for neuromorphic computing.