Talk by Dionisios Pnevmatikatos (Techn. Univ. Crete) : Reconfigurable Accelerator Architectures for Streaming applications @ MHL/TUC

11.01.2017 13:30

CAB F 72

Speaker: Dionisios Pnevmatikatos (Techn. Univ. Crete)


Reconfigurable Accelerator Architectures for Streaming applications @ MHL/TUC


At the Microprocessor a Hardware Laboratory of the Technical University of Crete we have a long track of research in reconfigurable accelerators. I will give a brief overview of our recent work on accelerators for intensive big-data (Classification and Frequent sub-graph mining), and then focus on accelerating streaming applications, namely Stream Join and (ECM) Exponential Sketch generation. These works have been designed and prototyped in the high-performance Convey HC-2 reconfigurable system. I will also offer a brief overview of current efforts in the same direction.

Short Bio:

Dionisios Pnevmatikatos is a Professor and former Chair of the Electronic and Computing Engineering Department, Technical University of Crete and a Researcher at the Computer Architecture and VLSI Systems (CARV) Laboratory of the Institute of Computer Science, FORTH in Greece. He received his B.Sc. degree in Computer Science from the Department of Computer Science, University of Crete in 1989 and M.Sc. and Ph.D. degrees in Computer Science from the Department of Computer Science, University of Wisconsin-Madison in 1991 and 1995 respectively. His research interests are in the broader area of Computer Architecture, where he investigates the Design and Implementation of High-Performance and Cost-Effective Systems, Reliable System Design, and Reconfigurable Computing. Within this context, he has performed research in Networking Hardware and Network Processors, Application Acceleration, Custom and Application-Specific Architectures, and Hardware Acceleration of Bioinformatics Algorithms. He has published several articles in international conferences and journals and has served on the program committees of numerous international conferences. He is the Program Co-Chair of the 21st International Conference on Field Programmable Logic and Applications (FPL), and was the Chair and Vice-Chair in the Architecture and Microarechitecture Track of the Design and Test Europe (DATE) conference in years 2007-2010. He was the General Co-Chair of the 2008 Panhellenic Conference on Informatics (PCI) and of the International Workshop on Rapid System Prototyping (RSP) in 2007, and has been a member of the Technical Program Committee in many of the key international conferences of his field. He is currently the Coordinator of the FASTER project (ICT, STREP) and has participated in numerous national and European projects. He is a member of IEEE.