FPGAs in the Datacenter

The limitations of today's computing architectures are well known: high power consumption, heat dissipation, network and I/O bottlenecks, and the memory wall. Field-programmable gate arrays (FPGAs), user-configurable hardware chips, are promising candidates to overcome these limitations. With tailor-made and software-configured hardware circuits it is possible to process data at very high throughput rates and with extremely low latency. Yet, FPGAs consume orders of magnitude less power than conventional systems. Thanks to their high configurability, they can be used as co-processor in heterogeneous multi-core architectures, and/or directly be placed in critical datapaths to reduce the load that hits the system CPU.

Current projects:

Past projects:

Current project members:

Former members:

  • Zeke Wang (Postdoc, now Assistant Professor at Zhejiang University, China)
  • Muhsen Owaida (Postdoc, now at SnowBell, Switzerland)
  • David Sidler (PhD graduate, now at Microsoft, USA)
  • René Müller (PhD graduate, now with FH Bern, Switzerland)
  • Jens Teubner (Postdoc, now Professor at TU Dortmund, Germany)
  • Louis Woods (PhD graduate, now with Apcera, USA)
  • Zsolt Istvan (PhD graduate, now Assistant Professor at IMDEA, Spain)


(For complete list please see each individual project)

Conference papers

  • Zhenhao He, Zeke Wang, Gustavo Alonso. BiS-KM: Enabling Any-Precision K-Means on FPGAs. 28th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA'20), Monterey, US.

Journal publications

Demos, Tutorials and Workshops


Our FPGA work is funded in part by grants from Xilinx, as part of the Enterprise Computing Center (www.ecc.ethz.ch), and Microsoft Research, as part of the Joint Research Center MSR-ETHZ-EPFL. We use FPGA equipment generously donated by Xilinx, by Intel through the Intel Altera Heterogeneous Research Platform, and acquired under the Maxeler University Program.