Network Acceleration


In this project we developed a scalable 10G TCP/IP for reconfigurable hardware. The stack supports up to 10,000 concurrent sessions enabling data center applications such as key value stores on the FPGA. The stack was further optimized based on application specific knowledge.

The source is available on github.

Data processing on the network card

Currently are extending the network stack with RDMA-capabilities, in particular RoCEv2, and also plan to increase the bandwidth to 25-40G. Th goal is to use the FPGA as a prototype platform for a network card and to deploy data processing along side network processing on the FPGA. As a result data can be processed while it is moving between main memory and the network or vice versa. With this prototype network card we want to identify functionality that can be offloaded and the corresponding applications that can benefit from this type of acceleration.



David Sidler, Zsolt Istvan, Gustavo Alonso.
26th International Conference on Field Programmable Logic and Applications (FPL), Lausanne, Switzerland, September 2016.
David Sidler, Gustavo Alonso, Michaela Blott, Kimon Karras, Kees Vissers, Raymond Carley.
23th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Vancouver, May 2015, [Slides].