MULTICORES

During the last few years, there have been radical changes in the hardware and the processor architecture landscape. Intel’s co-founder Gordon E. Moore’s famous conjecture that the number of transistors on integrated circuits doubles roughly every two years still holds today. However, multi-core processors caused a paradigm shift in hardware where increasing number of transistors are invested in parallelism and advanced features on chip designs. In addition to increasing core counts, sophisticated features like advanced instruction sets, SIMD instructions, simultaneous multi-threading (SMT), larger and multiple layers of caches are being introduced in the newer processor designs. All of these game-changing technological trends constitute the driving force behind how new data processing systems and algorithms should be designed and tailored today, albeit making it even more challenging. Moreover, as there are no established designs for the contemporary multicores, there is also no clear consensus on how to design data processing algorithms to take advantage of available features as well as suggest new features to the hardware architects. In this research area, we design novel hardware-conscious algorithms and systems that are targeted to the recent features in hardware to extract the performance premises of modern multi-core machines and which provide insights for upcoming generations of multicores.

In "Parallel Joins on Multi-Core" project we have investigated an extensive set of join approaches, both in terms of algorithms and implementations on a broad range of recent multi-core platforms. Our investigations have provided conclusive answers to the existing controversies in the literature. One of the existing debates on joins is whether hash join should be hardware-conscious or hardware-oblivious given the advances on the hardware side such as simultaneous multi-threading and automatic hardware prefetching. Our results indicate that hash join algorithms that are hardware-conscious perform generally better than the hardware-oblivious counterparts. On an algorithmic aspect, there has been controversies in the literature whether sort-merge joins or hash joins are now a better option due to features in new hardware such as wide SIMD instructions. In our study using most optimized versions of both sides, we have shown that hash joins still maintain an edge over sort-merge joins despite the advances on SIMD. Further details on Parallel Joins can be found here.

We have also looked at several data stream algorithms and proposed new solutions for approximate frequent item counting and stream joins for multi-cores that circumvent the limitations of existing solutions.

We have many available open projects which can be suitable for master thesis or lab projects. Please contact us if you are interested.

Current Project Members:

Past Project Members:

  • Cagri Balkesen (PhD graduate, now with Oracle Labs)
  • Daniela Dorneanu (PhD Student)
  • Jens Teubner (Senior researcher, now Professor at TU Dortmund)
  • Pratanu Roy (PhD graduate, now with Oracle Labs)

Publications

Conference Papers

  • Pratanu Roy, Jens Teubner, and Rainer Gemulla. Low-Latency Handshake Join. Proc. of the VLDB Endowment (PVLDB), Volume 7 (9), Hangzhou, China, 2014.

Journal Papers

Demos, Tutorials, Workshops and Technical Reports

  • Cagri Balkesen, Louis Woods, and Jens Teubner. New Hardware Architectures for Data Management. 15. GI-Fachtagung für Business, Technologie und Web (BTW 2013), Tutorial, Magdeburg, Germany, March 2013.

 


 

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