Spring 2017

Time and Location

The lunch seminar is held every Friday from 12:15 to 13:15h at CAB E 72 (lunch provided at 12:00).

Lunch Seminar organizers:

Renato Marroquin, Lukas Humbel, Konstantin Taranov, Debopam Bhattacherjee


The topic will be announced shortly before the talk.

Date Speaker Institute Topic Food
24.02.2017 Markus Pilman Snowflake Computing Snowflake - A Data Warehouse built for the Cloud

Ingo Muller


03.03.2017 Vasiliki Kalavri Systems Group Introduction to Apache Flink

Reto Achermann


10.03.2017 Tal Ben Nun Systems Group Memory Access Patterns: The Missing Piece of the GPU Programming Puzzle

Claude Barthels


17.03.2017 Hasan Hasan Systems Group  DRAM Latency Reduction

 Darko Makreshanski

(Grune Lebanon)


Satoshi Matsuoka


Tokyo Institute of Technology FLOPS to BYTES: Accelerating Beyond Moore's Law Roni Häcki 

Aya Fukami

1:00 pm

Carnegie Mellon University

Improving the Reliability of Chip-Off Forensic Analysis of NAND Flash Memory Devices

31.03.2017 Petar Tsankov Information Security Group Programmable Networks with Synthesis Kaan Kara
07.04.2017 Lois Orosa     Gerd Zellweger
14.04.2017 Good Friday Holiday    
21.04.2017 Darko Makreshanski Systems Group    
28.04.2017 Vojslav Dukic Systems Group   Maciej Besta
05.05.2017 Dimitar Dimitrov Software Reliability Lab Serializability for Eventual Consistency: Criterion, Analysis, and Applications (POPL 2017)  
12.05.2017 Alexandr Nigay Systems Group   Sebastian Wicki
19.05.2017 Salvatore Di Girolamo Systems Group   Moritz Hoffmann
26.05.2017 Debopam Bhattacherjee Systems Group   Zaheer Chothia


Fall 2016

Time and Location

The lunch seminar is held every Friday from 12:15 to 13:15h at CAB E 72 (lunch provided at 12:00).

Lunch Seminar organizers:

Kaan Kara, Roni Häcki, Claude Barthels and Maciej Besta


The topic will be announced shortly before the talk.

Date Speaker Institute Topic Food
 23.09.  Claude Barthels  Systems Group  Distributed Joins on a Thousand Cores  Ingo Müller (Bagels)
 30.09.  Tim Harris  Oracle Labs  What does the operating system ever do for me?
 David Sidler (Pizza)
 07.10.  Zsolt István  Systems Group

Don’t let the size fool you! Smart distributed storage on specialized

 Lucas Braun (Pie)

 14.10.  Torsten Hoefler  Systems Group

Scientific Benchmarking of Parallel Computing Systems

 Jana Giceva


 21.10.  Desi Dimitrova  Systems Group

Citius, Altius, Fortius: What a network controller should be?

 Simon Gerber


 28.10.  Maciej Besta  Systems Group High-Performance Distributed RMA Locks  Zaheer Chothia
 04.11.  Leo Tam  NVIDIA NVIDIA - Research  Sabela Ramos (Bagels)
 11.11.  Dan Alistarh  ETH Zurich

Architectural Support for Scalable Concurrent Data Structures

 David Cock

 18.11. Antonio Carzinaga USI Lugano

Descriptors, Locators, Identifiers:

Multi-Modal Addressing in the TagNet Information-Centric Networking Architecture

 Desi Dimitrova

 25.11.  Andreas Gerstlauer  UT Austin

Learning-Based System-Level Power and Performance Prediction

 Konstantin Taranov

 02.12.  Lukas Humbel  Systems Group Modeling interrupt systems  Vojislav Dukic (Pie)
 09.12.  Ji Liu University of Rochester Asynchronous parallel optimization for large scale machine learning  Gerd Zellweger (Döner)
 16.12.  Renato Marroquin  Systems Group

READY: Completeness is in the Eye of the Beholder

 Arash Tavakkol


Thesis/Lab Projects Descriptions

Masters/Semester/Lab Projects

 Master Thesis Projects: 

  • Automatic Detection of Web Trackers in Real-Time (pdf)

  • Incremental computation and maintenance of the metric backbone for fast graph analytics (pdf)

  • PySpark at Bare-Metal Speed (pdf)

  • Exploiting Graph Traversal Algorithms for Network Resilience (pdf)

  • MineLiB: A Library of Sub-Operators for Data Mining Algorithms (pdf)

  • Multiple Query Execution (pdf)

  • Late Materialization for Join Processing (pdf)

  • The Evolution of Latency on the Internet (pdf)

  • How Much Does the Data Center Network Really Matter? (pdf)

  • Online gaming at the speed of light (pdf)

  • Short-circuiting Internet routing (pdf)

  •  Performance Analysis of Data Analytics Applications on Scale-out Architectures (pdf

  • Designing and Building a Cloud-based ISP (pdf)

  • Worst-case Optimal Join Algorithms for SPARQL Query Evaluation (pdf)

 Bachelor Thesis Projects:

  • Jump the Queue: Installing Open Flow Rules for Multiples Hops (pdf)



Spring 2016

Time and Location

The lunch seminar is held every Friday from 12:15 to 13:15h at CAB E 72 (lunch provided at 12:00).

Lunch Seminar organizers:

Stefan Kaestle, Anja Gruenheid, David Sidler, Sabela Ramos


The topic will be announced shortly before the talk.

Date Speaker Institute Topic Food

Reto Achermann,

Stefan Kaestle


Smelt: Machine-aware Atomic Broadcast Trees for Multicores

 Haecki, Roni (Bagels)
 04.03.2016 Ingo Müller  SG

Engineering Aggregation Operators for Relational In-Memory Database Systems (PhD Thesis)

 Gysi, Tobias (Pizza)
 11.03.2016 Onur Kocberber  Oracle Labs  Accelerators for Data Processing (PhD Thesis)  Kara, Kaan (Libanese Sandwiches)
 18.03.2016  John Liagouris  SG Explaining Outputs in Modern Data Analytics Nushi, Besmira (Hot Pasta)
 25.03.2016 Good Friday      
 01.04.2016 5 Minute Madness     5 Minute Madness   Marroquin, Renato (Döner)
 08.04.2016 Arthur Grevias  System Security Tampering with the Delivery of Blocks and Transactions in Bitcoin Achermann, Reto (Nordsee)

Zaheer Chothia

 SG Realising real-time session reconstruction   Humbel, Lukas (Pizza)

Maciej Besta

 SG Accelerating Irregular Computations with HardwareTransactional Memory and Active Messages  Di Girolamo, Salvatore (Bagels)
 29.04.2016 Desislava Dimitrova  SG Program me a network  Schneider, Timo (Pasta)
 06.05.2016 David Cock  SG Litmus Testing at Rack Scale  Liagouris, John (Turkish Pizza)

Grzegorz Kwasniewski

 SG A PCIe Congestion-Aware Performance Model for Densely Populated Accelerator Servers

Makreshanski, Darko (Döner)

 20.05.2016 Muhsen Owaida  SG Database Acceleration on CPU-FPGA Shared Memory Platforms Grosser, Tobias (Bagels)
 27.05.2016 Philipp Miedl  TIK On the Capacity of Thermal Covert Channels in Multicores Besta, Maciej
 03.06.2016 Timo Schneider  SG   Owaida, Muhsen


Fall 2015

Time and Location

The lunch seminar is held every Friday from 12:15 to 13:15h at CAB E 72 (lunch provided at 12:00).


Lunch Seminar organizers:

Jonas Pfefferle, Moritz Hoffmann, Besmira Nushi, Tobias Grosser


The topic will be announced shortly before the talk.

Date Speaker Institute Topic Food


Frank McSherry


Differential Dataflow

Kaestle, Stefan (Pizza)


Raychev Veselin


Parallelizing User-Defined Aggregations using Symbolic Execution

Zellweger, Gerd


Lucas Braun


MTSQL - A Relational Algebra for Multi-Tenancy

Barthels, Claude (Bagels)


Arijit Khan


Querying Big-graphs - Streaming and Beyond

Marroquin, Renato  (Doner)


5 Minute Madness


Zsolt Istvan, Edgar Solomonik, David Sidler, Zaheer Chothia, Sabela Ramos, Grzegorz Kwasniewski

Sidler, David (PizzaLemon)


Tobias Gysi


STELLA: A Domain-specific Tool for Structured Grid Methods in Weather and Climate Models

Chothia, Zaheer (Hot Pasta)





István, Zsolt (NordSee)


Akhi Singhania


Unleashing the performance of 10G NICs

Mueller, Stefan (Bagels)


Simon Gerber


Cichlid: Explicit physical memory management for large machines

Shinde, Pravin (LebaneseWrap)


Gerd Zellweger


SpaceJMP: Programming with Multiple Virtual Address Spaces

Roy, Pratanu (PizzaDieci)


Besmira Nushi


Crowdsourcing Component-based Error Diagnosis of Intelligent Systems

Makreshanski, Darko (HotPasta)


Pierre-Evariste Dagand


 Programming with Streams

Giceva, Jana


5 minute madness


 Desislava Dimitrova, Markus Pilman, Renato Marroquin, Moritz Hoffman, David Stolz, Timo Schneider

Gerber, Simon (Bagels)


Jana Giceva


Basslet: OS support for parallel data processing on modern multi-cores

Braun, Lucas


Data Processing on Modern Hardware


The limitations of today's computing architectures are well known: high power consumption, heat dissipation, network and I/O bottlenecks, and the memory wall. Field-programmable gate arrays (FPGAs), user-configurable hardware chips, are promising candidates to overcome these limitations. With tailor-made and software-configured hardware circuits it is possible to process data at very high throughput rates and with extremely low latency. Yet, FPGAs consume orders of magnitude less power than conventional systems. Thanks to their high configurability, they can be used as co-processors in heterogeneous multi-core architectures, and/or directly be placed in critical data paths to reduce the load that hits the system CPU. More...



During the last few years, there have been radical changes in the hardware and the processor architecture landscape. Intel’s co-founder Gordon E. Moore’s famous conjecture that the number of transistors on integrated circuits doubles roughly every two years still holds today. However, multi-core processors caused a paradigm shift in hardware where increasing number of transistors are invested in parallelism and advanced features on chip designs. In addition to increasing core counts, sophisticated features like advanced instruction sets, SIMD instructions, simultaneous multi-threading (SMT), larger and multiple layers of caches are being introduced in the newer processor designs. All of these game-changing technological trends constitute the driving force behind how new data processing systems and algorithms should be designed and tailored today, albeit making it even more challenging. Moreover, as there are no established designs for the contemporary multicores, there is also no clear consensus on how to design data processing algorithms to take advantage of available features as well as suggest new features to the hardware architects. In this research area, we design novel hardware-conscious algorithms and systems that are targeted to the recent features in hardware to extract the performance premises of modern multi-core machines and which provide insights for upcoming generations of multicores. More... 


Rack-scale data processing system

We are building a data appliance for Rack-scale Computers (RaSC) that leverages the benefits of cross-layer optimization and provides support for heterogeneous workloads. To achieve that we separate the storage from the data processing layer. The two layers communicate over a scalable interconnect fabric, at the moment focusing on RDMA over InfiniBand. More...

Back to Research