Time and Location

The lunch seminar is held every Friday from 12:15 to 13:15 at CAB E 72.

Lunch Seminar organizers:

Vasiliki Kalavri, Melissa Licciardello, Shaoduo Gan, Sabir Akhadov

The topic will be announced shortly before the talk.

The Computing Platforms Seminar Series (COMPASS) is focused on talks by industry and academia around the general topic of computing platforms.

COMPASS is held on most Thursdays during the semester 10:00-11:00 (with some exceptions) in CAB E 72.

Upcoming Talks:

Wednesday, 15 August 2018, 11:00-12:00 in CAB E 72

Speaker: Leonid Yavits (Technion)

Title: Resistive CAM based architectures: Resistive Associative In-Storage Processor and Resistive Address Decoder

Abstract:

I will present two Resistive CAM (RCAM) based architectures:

Typical processing in storage architecture places processing cores inside storage system and allows near-data processing. A RCAM based Resistive Associative In-Storage Processor functions simultaneously as a storage and a massively parallel SIMD accelerator. It confines the computing to the storage arrays, thus implementing in-data rather than near-data processing. Resistive Associative In-Storage Processor outperforms the fastest state of art accelerators, achieving speedup of 9.7x, 5.1x, 3.5x and 2.9x for k-means, k-nearest neighbors, Smith-Waterman sequence alignment and fully connected layer of DNN, respectively.

Address decoders are typically hardwired. Replacing wires by resistive elements allows storing address alongside data and comparing it to input address, thus transforming address decoder into CAM and enabling fully associative access. Applications of resistive address decoder include fully associative TLB, cache and virtually addressable memory.

Bio: 

Leonid Yavits received his MSc and PhD in Electrical Engineering from the Technion. After graduating, he co-founded VisionTech where he co-designed the world's first single chip MPEG2 codec. Following VisionTech’s acquisition by Broadcom, he managed Broadcom Israel R&D and co-developed a number of video compression products. Later Leonid co-founded Horizon Semiconductors where he co-designed a Set Top Box-on-chip for cable and satellite TV. Horizon's chip was among world's earliest heterogeneous MPSoC.

Leonid is a postdoc fellow in Electrical Engineering in the Technion. He co-authored a number of patents and research papers. His research interests include non von Neumann computer architectures; processing in memory and resistive memory based computing; architectures for computational biology and bioinformatics tasks. Leonid's research work has earned several awards; among them: IEEE Computer Architecture Letter journal Best Paper Awards for 2015 and 2017.

FALL SEMESTER 2018

Thursday, 20 September, 10:00-11:00 in CAB E 72

Speaker: Patrick Stüdi (IBM Research)

Title: TBA

Abstract: TBA

Thursday, 4 October 2018, 10:00-11:00 in CAB E 72

Speaker: Philippe Bonnet (IT University, Copenhagen, Denmark)

Title: TBA

Abstract: TBA

Past COMPASS Talks:  

Time and Location

The lunch seminar is held every Friday from 12:15 to 13:15h at CAB E 72 (lunch provided at 12:00).

Lunch Seminar organizers:

Renato Marroquin, Lukas Humbel, Konstantin Taranov, Debopam Bhattacherjee

The topic will be announced shortly before the talk.

 Centaur

Time and Location

The lunch seminar is held every Friday from 12:15 to 13:15 at CAB E 72.

Lunch Seminar organizers:

Hantian Zhang, Alexandros Ziogas, Lukas Arnold, Hasan Hassan

The topic will be announced shortly before the talk.

Time and Location

The lunch seminar is held every Friday from 12:15 to 13:15h at CAB E 72 (lunch provided at 12:00).

Lunch Seminar organizers:

Kaan Kara, Roni Häcki, Claude Barthels and Maciej Besta

The topic will be announced shortly before the talk.

Masters/Semester/Lab Projects

 Master Thesis Projects: 

• Satellite-based low-latency Internet [MT/BT] (pdf)

• De-anonymizing encrypted video streams [MT] (pdf)

• Deconstructing YouTube's secret sauce [MT] (pdf)

• DS3 Lab Project Proposals (Mashine Learning, NLP/Computer Vision...)

• Making machine learning friendlier in the cloud [MT] (pdf)

• Bringing circuits switching back from the dead [MT] (pdf)

• Navigating the Main Memory Landscape with Fast and Novel Infrastructures  [MT or BT] (pdf)

• Evaluating and Enabling Processing inside Memory [MT or BT] (pdf)

• Designing and Evaluating Energy-Efficient Main Memory (MT/BT/Semester Project) (pdf)

• Parameter-free data center networking [MT or BT] (pdf)

• Turning Web page delivery upside down [MT or BT] (pdf)

• The future of data center networks: static v. dynamic  [MT or BT] (pdf)

• Quantifying the cost of network policy [MT or BT] (pdf)

• Incremental computation and maintenance of the metric backbone for fast graph analytics (pdf)

• Exploiting Graph Traversal Algorithms for Network Resilience (pdf)

• MineLiB: A Library of Sub-Operators for Data Mining Algorithms (pdf)

• Online OS Profiling wiht SnailTrail [MT] (pdf)

• How quick could QUIC be? [MT or BT] (pdf)

• Worst-case Optimal Join Algorithms for SPARQL Query Evaluation (pdf)

• How un/fair is the Internet? [MT or BT] (pdf)

• How much does the DC network really matter? [MT or BT] (pdf)

 Bachelor Thesis Projects

See proposals marked [MT or BT] above.

Time and Location

The lunch seminar is held every Friday from 12:15 to 13:15h at CAB E 72 (lunch provided at 12:00).

Lunch Seminar organizers:

Stefan Kaestle, Anja Gruenheid, David Sidler, Sabela Ramos

The topic will be announced shortly before the talk.

Time and Location

The lunch seminar is held every Friday from 12:15 to 13:15h at CAB E 72 (lunch provided at 12:00).

Lunch Seminar organizers:

Jonas Pfefferle, Moritz Hoffmann, Besmira Nushi, Tobias Grosser

The topic will be announced shortly before the talk.

FPGA

The limitations of today's computing architectures are well known: high power consumption, heat dissipation, network and I/O bottlenecks, and the memory wall. Field-programmable gate arrays (FPGAs), user-configurable hardware chips, are promising candidates to overcome these limitations. With tailor-made and software-configured hardware circuits it is possible to process data at very high throughput rates and with extremely low latency. Yet, FPGAs consume orders of magnitude less power than conventional systems. Thanks to their high configurability, they can be used as co-processors in heterogeneous multi-core architectures, and/or directly be placed in critical data paths to reduce the load that hits the system CPU. More...

MULTICORES 

During the last few years, there have been radical changes in the hardware and the processor architecture landscape. Intel’s co-founder Gordon E. Moore’s famous conjecture that the number of transistors on integrated circuits doubles roughly every two years still holds today. However, multi-core processors caused a paradigm shift in hardware where increasing number of transistors are invested in parallelism and advanced features on chip designs. In addition to increasing core counts, sophisticated features like advanced instruction sets, SIMD instructions, simultaneous multi-threading (SMT), larger and multiple layers of caches are being introduced in the newer processor designs. All of these game-changing technological trends constitute the driving force behind how new data processing systems and algorithms should be designed and tailored today, albeit making it even more challenging. Moreover, as there are no established designs for the contemporary multicores, there is also no clear consensus on how to design data processing algorithms to take advantage of available features as well as suggest new features to the hardware architects. In this research area, we design novel hardware-conscious algorithms and systems that are targeted to the recent features in hardware to extract the performance premises of modern multi-core machines and which provide insights for upcoming generations of multicores. More... 

Rack-scale data processing system

We are building a data appliance for Rack-scale Computers (RaSC) that leverages the benefits of cross-layer optimization and provides support for heterogeneous workloads. To achieve that we separate the storage from the data processing layer. The two layers communicate over a scalable interconnect fabric, at the moment focusing on RDMA over InfiniBand. More...

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