Research

Fall 2018


Time and Location

The lunch seminar is held every Friday from 12:15 to 13:15 at CAB E 72.

Lunch Seminar organizers:

Vasiliki Kalavri, Melissa Licciardello, Shaoduo Gan, Sabir Akhadov

 

The topic will be announced shortly before the talk.

Date Speaker Institute Topic Food
         
     
     
     
         
     
     
         
         
         
         
     
         
         
         
     
     
         
         
     
         
         

 

Computing Platforms Seminar Series (COMPASS)

The Computing Platforms Seminar Series (COMPASS) is focused on talks by industry and academia around the general topic of computing platforms.

COMPASS is held on most Thursdays during the semester 10:00-11:00 (with some exceptions) in CAB E 72.

Upcoming Talks:

Wednesday, 15 August 2018, 11:00-12:00 in CAB E 72

Speaker: Leonid Yavits (Technion)

Title: Resistive CAM based architectures: Resistive Associative In-Storage Processor and Resistive Address Decoder

 

 

Abstract:

I will present two Resistive CAM (RCAM) based architectures:

Typical processing in storage architecture places processing cores inside storage system and allows near-data processing. A RCAM based Resistive Associative In-Storage Processor functions simultaneously as a storage and a massively parallel SIMD accelerator. It confines the computing to the storage arrays, thus implementing in-data rather than near-data processing. Resistive Associative In-Storage Processor outperforms the fastest state of art accelerators, achieving speedup of 9.7x, 5.1x, 3.5x and 2.9x for k-means, k-nearest neighbors, Smith-Waterman sequence alignment and fully connected layer of DNN, respectively.

Address decoders are typically hardwired. Replacing wires by resistive elements allows storing address alongside data and comparing it to input address, thus transforming address decoder into CAM and enabling fully associative access. Applications of resistive address decoder include fully associative TLB, cache and virtually addressable memory.

Bio: 

Leonid Yavits received his MSc and PhD in Electrical Engineering from the Technion. After graduating, he co-founded VisionTech where he co-designed the world's first single chip MPEG2 codec. Following VisionTech’s acquisition by Broadcom, he managed Broadcom Israel R&D and co-developed a number of video compression products. Later Leonid co-founded Horizon Semiconductors where he co-designed a Set Top Box-on-chip for cable and satellite TV. Horizon's chip was among world's earliest heterogeneous MPSoC.

Leonid is a postdoc fellow in Electrical Engineering in the Technion. He co-authored a number of patents and research papers. His research interests include non von Neumann computer architectures; processing in memory and resistive memory based computing; architectures for computational biology and bioinformatics tasks. Leonid's research work has earned several awards; among them: IEEE Computer Architecture Letter journal Best Paper Awards for 2015 and 2017.


FALL SEMESTER 2018


Thursday, 20 September, 10:00-11:00 in CAB E 72

Speaker: Patrick Stüdi (IBM Research)

Title: TBA

Abstract: TBA


Thursday, 4 October 2018, 10:00-11:00 in CAB E 72

Speaker: Philippe Bonnet (IT University, Copenhagen, Denmark)

Title: TBA

Abstract: TBA


 

Past COMPASS Talks:  

Date Speaker Affiliation Talk
06.07.2018 Martin Burtscher Texas State University Automatic Hierarchical Parallelization of Linear Recurrences
15.06.2018 Nitin Agrawal Samsung Research Low-Latency Analytics on Colossal Data Streams with SummaryStore
24.05.2018 Cagri Balkesen Oracle Labs RAPID: In-Memory Analytical Query Processing Engine with Extreme Performance per Watt
16.05.2018 Carsten Binnig TU Darmstadt Towards Interactive Data Exploration
09.05.2018 Bastian Hossbach Oracle Labs Modern programming languages and code generation in the Oracle Database
26.04.2018 Spyros Blanas Ohio State University Scaling database systems to high-performance computers
19.04.2018 Jane Hung MIT The Challenges and Promises of Large-Scale Biological Imaging
12.04.2018 Christoph Hagleitner IBM Research Heterogeneous Computing Systems for Datacenter and HPC Applications
14.03.2018  Eric Sedlar
 Oracle Labs
Why Systems Research Needs Social Science Added to the Computer Science
01.03.2018 Saughata Ghose Carnegie Mellon University How Safe Is Your Storage? A Look at the Reliability and Vulnerability of Modern Solid-State Drives
22.02.2018  Ioannis Koltsidas IBM Research Zurich System software for commodity solid-state storage
       
       
       
       
       

 


 

Spring 2017


Time and Location

The lunch seminar is held every Friday from 12:15 to 13:15h at CAB E 72 (lunch provided at 12:00).

Lunch Seminar organizers:

Renato Marroquin, Lukas Humbel, Konstantin Taranov, Debopam Bhattacherjee

 

The topic will be announced shortly before the talk.

Date Speaker Institute Topic Food
24.02.2017 Markus Pilman Snowflake Computing Snowflake - A Data Warehouse built for the Cloud

Ingo Muller

(Bagels)

03.03.2017 Vasiliki Kalavri Systems Group Introduction to Apache Flink

Reto Achermann

(Pizza)

10.03.2017 Tal Ben Nun Systems Group Memory Access Patterns: The Missing Piece of the GPU Programming Puzzle

Claude Barthels

(Nordsee)

17.03.2017 Hasan Hasan Systems Group  DRAM Latency Reduction

 Darko Makreshanski

(Grune Lebanon)

24.03.2017

Satoshi Matsuoka

12:15pm

Tokyo Institute of Technology FLOPS to BYTES: Accelerating Beyond Moore's Law Roni Häcki 

Aya Fukami

1:00 pm

Carnegie Mellon University

Improving the Reliability of Chip-Off Forensic Analysis of NAND Flash Memory Devices

 
31.03.2017 Petar Tsankov Information Security Group Programmable Networks with Synthesis Kaan Kara
07.04.2017 Aanjhan Ranganathan System Security Group Securing Next-generation Autonomous Cyber-physical Systems Moritz Hoffmann 
14.04.2017 Good Friday Holiday    
21.04.2017 Darko Makreshanski Systems Group BatchDB: Efficient Isolated Execution of Hybrid OLTP+OLAP Workloads for Interactive Applications Gerd Zellweger
28.04.2017 Debopam Bhattacherjee Systems Group A Cloud-based Content Gathering Network Maciej Besta
05.05.2017 Dimitar Dimitrov Software Reliability Lab Serializability for Eventual Consistency: Criterion, Analysis, and Applications (POPL 2017) Salvatore Di Girolamo
12.05.2017 Alexandr Nigay Systems Group Exploring the idea of virtualizing MPI Sebastian Wicki
19.05.2017 Vojslav Dukic Systems Group Datacenter oracle: Predicting Resource Usage Inside a Data Center  Yaohua Wang
26.05.2017 Salvatore Di Girolamo Systems Group Transparent Caching for RMA Systems

Zaheer Chothia

        

 

Centaur

 Centaur

Spring 2018


Time and Location

The lunch seminar is held every Friday from 12:15 to 13:15 at CAB E 72.

Lunch Seminar organizers:

Hantian Zhang, Alexandros Ziogas, Lukas Arnold, Hasan Hassan

 

The topic will be announced shortly before the talk.

Date Speaker Institute Topic Food
 23 February

David Dao

Systems Group

AI, meet blockchain - Towards machine learning markets Roni Häcki (Bagel)
Niels Gleinig Systems Group Algebraic analysis of directed graphs
Melissa Licciardello Systems Group Adaptive Bitrate on Video Streaming: a reliable comparison 
Bojan Karlas Systems Group Introduction
 2 March

Sabir Akhadov

Systems Group 

Pyspark at bare-metal speed David Sidler (Pizza)
Johannes Rausch Systems Group Introduction
Kaveh Razavi Vrije Universiteit Amsterdam Introduction
 9 March Thomas Lemmin Systems Group Spectral Analysis of Fluorescently Labeled Amyloids Zaheer Chothia (Pizza)
 16 March Tal Ben Nun Systems Group Stateful Dataflow Multigraphs: A Data-Centric Bridge between Imperative and Spatial Programming Kaan Kara (Pizza)
23 March  David Cock Systems Group The Status of the Enzian Project Jeremie Kim (Pasta)
 13 April Konstantin Taranov Systems Group Fast and strongly-consistent per-item resilience in key-value stores Lukas Arnold (Sausage/ Tofu with potato salad)
Nora Hollenstein Systems Group & IBM Natural Language Processing @ DS3Lab
 20 April Gustavo Sutter Universidad Autónoma de Madrid Network traffic monitoring in multi-gigabit Ethernet  Alexandr Nigay (Bagel)
 27 April Can Alkan Bilkent University Characterization of genome structural variation and large inversions using high throughput sequencing Claude Barthels (Wraps)
 4 May

Lukas On Arnold

Systems Group 

Covariance Matrix Calculation on a Hybrid FPGA/CPU System Melissa Licciardello (Pizza)
Marcin Copik Systems Group Introduction
Cédric Renggli Systems Group Introduction
11 May  Maciej Besta Systems Group To Push or To Pull: On Reducing Communication and Synchronzation in Graph Computations Merve Gürel (Dürüm)
 18 May

David Sidler

Systems Group 

Processing-in-Network (PIN): A programmable NIC for data processing offloading Konstantin Taranov (Pizza)
Amit Kulkarni Systems Group Introduction
 25 May Arash Tavakkol Systems Group FLIN: Enabling Fairness and Enhancing Performance in Modern NVMe Solid State Drives Shaoduo Gan (Falafel)
 1 June Arseniy Zaostrovnykh EPFL A Formally Verified NAT J. de Fine Licht (Wraps)

 

Fall 2016


Time and Location

The lunch seminar is held every Friday from 12:15 to 13:15h at CAB E 72 (lunch provided at 12:00).

Lunch Seminar organizers:

Kaan Kara, Roni Häcki, Claude Barthels and Maciej Besta

 

The topic will be announced shortly before the talk.

Date Speaker Institute Topic Food
 23.09.  Claude Barthels  Systems Group  Distributed Joins on a Thousand Cores  Ingo Müller (Bagels)
 30.09.  Tim Harris  Oracle Labs  What does the operating system ever do for me?
 David Sidler (Pizza)
 07.10.  Zsolt István  Systems Group

Don’t let the size fool you! Smart distributed storage on specialized
hardware.

 Lucas Braun (Pie)

 14.10.  Torsten Hoefler  Systems Group

Scientific Benchmarking of Parallel Computing Systems

 Jana Giceva

(Nordsee)

 21.10.  Desi Dimitrova  Systems Group

Citius, Altius, Fortius: What a network controller should be?

 Simon Gerber

(Döner)

 28.10.  Maciej Besta  Systems Group High-Performance Distributed RMA Locks  Zaheer Chothia
 04.11.  Leo Tam  NVIDIA NVIDIA - Research  Sabela Ramos (Bagels)
 11.11.  Dan Alistarh  ETH Zurich

Architectural Support for Scalable Concurrent Data Structures

 David Cock
(Döner)

 18.11. Antonio Carzinaga USI Lugano

Descriptors, Locators, Identifiers:

Multi-Modal Addressing in the TagNet Information-Centric Networking Architecture

 Desi Dimitrova
(Sandwich)

 25.11.  Andreas Gerstlauer  UT Austin

Learning-Based System-Level Power and Performance Prediction

 Konstantin Taranov
(Pizza)

 02.12.  Lukas Humbel  Systems Group Modeling interrupt systems  Vojislav Dukic (Pie)
 09.12.  Ji Liu University of Rochester Asynchronous parallel optimization for large scale machine learning  Gerd Zellweger (Döner)
 16.12.  Renato Marroquin  Systems Group

READY: Completeness is in the Eye of the Beholder

 Arash Tavakkol

 

Thesis/Lab Projects Descriptions

Masters/Semester/Lab Projects


 Master Thesis Projects: 

  • Satellite-based low-latency Internet [MT/BT] (pdf)

  • De-anonymizing encrypted video streams [MT] (pdf)

  • Deconstructing YouTube's secret sauce [MT] (pdf)

  • DS3 Lab Project Proposals (Mashine Learning, NLP/Computer Vision...)

  • Making machine learning friendlier in the cloud [MT] (pdf)

  • Bringing circuits switching back from the dead [MT] (pdf)

  • Navigating the Main Memory Landscape with Fast and Novel Infrastructures  [MT or BT] (pdf)

  • Evaluating and Enabling Processing inside Memory [MT or BT] (pdf)

  • Designing and Evaluating Energy-Efficient Main Memory (MT/BT/Semester Project) (pdf)

  • Parameter-free data center networking [MT or BT] (pdf)

  • Turning Web page delivery upside down [MT or BT] (pdf)

  • The future of data center networks: static v. dynamic  [MT or BT] (pdf)

  • Quantifying the cost of network policy [MT or BT] (pdf)

  • Incremental computation and maintenance of the metric backbone for fast graph analytics (pdf)

  • Exploiting Graph Traversal Algorithms for Network Resilience (pdf)

  • MineLiB: A Library of Sub-Operators for Data Mining Algorithms (pdf)

  • Online OS Profiling wiht SnailTrail [MT] (pdf)

  • How quick could QUIC be? [MT or BT] (pdf)

  • Worst-case Optimal Join Algorithms for SPARQL Query Evaluation (pdf)

  • How un/fair is the Internet? [MT or BT] (pdf)

  • How much does the DC network really matter? [MT or BT] (pdf)


 Bachelor Thesis Projects

See proposals marked [MT or BT] above.


 


 

Spring 2016


Time and Location

The lunch seminar is held every Friday from 12:15 to 13:15h at CAB E 72 (lunch provided at 12:00).

Lunch Seminar organizers:

Stefan Kaestle, Anja Gruenheid, David Sidler, Sabela Ramos

 

The topic will be announced shortly before the talk.

Date Speaker Institute Topic Food
 26.02.2016

Reto Achermann,

Stefan Kaestle

 SG

Smelt: Machine-aware Atomic Broadcast Trees for Multicores

 Haecki, Roni (Bagels)
 04.03.2016 Ingo Müller  SG

Engineering Aggregation Operators for Relational In-Memory Database Systems (PhD Thesis)

 Gysi, Tobias (Pizza)
 11.03.2016 Onur Kocberber  Oracle Labs  Accelerators for Data Processing (PhD Thesis)  Kara, Kaan (Libanese Sandwiches)
 18.03.2016  John Liagouris  SG Explaining Outputs in Modern Data Analytics Nushi, Besmira (Hot Pasta)
 25.03.2016 Good Friday      
 01.04.2016 5 Minute Madness     5 Minute Madness   Marroquin, Renato (Döner)
 08.04.2016 Arthur Grevias  System Security Tampering with the Delivery of Blocks and Transactions in Bitcoin Achermann, Reto (Nordsee)
 15.04.2016

Zaheer Chothia

 SG Realising real-time session reconstruction   Humbel, Lukas (Pizza)
 22.04.2016

Maciej Besta

 SG Accelerating Irregular Computations with HardwareTransactional Memory and Active Messages  Di Girolamo, Salvatore (Bagels)
 29.04.2016 Desislava Dimitrova  SG Program me a network  Schneider, Timo (Pasta)
 06.05.2016 David Cock  SG Litmus Testing at Rack Scale  Liagouris, John (Turkish Pizza)
 13.05.2016

Grzegorz Kwasniewski

 SG A PCIe Congestion-Aware Performance Model for Densely Populated Accelerator Servers

Makreshanski, Darko (Döner)

 20.05.2016 Muhsen Owaida  SG Database Acceleration on CPU-FPGA Shared Memory Platforms Grosser, Tobias (Bagels)
 27.05.2016 Philipp Miedl  TIK On the Capacity of Thermal Covert Channels in Multicores Besta, Maciej
 03.06.2016 Timo Schneider  SG   Owaida, Muhsen

 

Fall 2015


Time and Location

The lunch seminar is held every Friday from 12:15 to 13:15h at CAB E 72 (lunch provided at 12:00).

 

Lunch Seminar organizers:

Jonas Pfefferle, Moritz Hoffmann, Besmira Nushi, Tobias Grosser

 

The topic will be announced shortly before the talk.

Date Speaker Institute Topic Food

18.09.2015

Frank McSherry

SG

Differential Dataflow

Kaestle, Stefan (Pizza)

25.09.2015

Raychev Veselin

SPCL

Parallelizing User-Defined Aggregations using Symbolic Execution

Zellweger, Gerd

02.10.2015

Lucas Braun

SG

MTSQL - A Relational Algebra for Multi-Tenancy

Barthels, Claude (Bagels)

09.10.2015

Arijit Khan

SG

Querying Big-graphs - Streaming and Beyond

Marroquin, Renato  (Doner)

16.10.2015

5 Minute Madness

SG

Zsolt Istvan, Edgar Solomonik, David Sidler, Zaheer Chothia, Sabela Ramos, Grzegorz Kwasniewski

Sidler, David (PizzaLemon)

23.10.2015

Tobias Gysi

SPCL

STELLA: A Domain-specific Tool for Structured Grid Methods in Weather and Climate Models

Chothia, Zaheer (Hot Pasta)

30.10.2015

 

 

 

István, Zsolt (NordSee)

06.11.2015

Akhi Singhania

 

Unleashing the performance of 10G NICs

Mueller, Stefan (Bagels)

13.11.2015

Simon Gerber

SG

Cichlid: Explicit physical memory management for large machines

Shinde, Pravin (LebaneseWrap)

20.11.2015

Gerd Zellweger

SG

SpaceJMP: Programming with Multiple Virtual Address Spaces

Roy, Pratanu (PizzaDieci)

27.11.2015

Besmira Nushi

SG

Crowdsourcing Component-based Error Diagnosis of Intelligent Systems

Makreshanski, Darko (HotPasta)

04.12.2015

Pierre-Evariste Dagand

SG

 Programming with Streams

Giceva, Jana
(Nordsee)

11.12.2015

5 minute madness

 

 Desislava Dimitrova, Markus Pilman, Renato Marroquin, Moritz Hoffman, David Stolz, Timo Schneider

Gerber, Simon (Bagels)

18.12.2015

Jana Giceva

SG

Basslet: OS support for parallel data processing on modern multi-cores

Braun, Lucas

 

Data Processing on Modern Hardware

FPGA

The limitations of today's computing architectures are well known: high power consumption, heat dissipation, network and I/O bottlenecks, and the memory wall. Field-programmable gate arrays (FPGAs), user-configurable hardware chips, are promising candidates to overcome these limitations. With tailor-made and software-configured hardware circuits it is possible to process data at very high throughput rates and with extremely low latency. Yet, FPGAs consume orders of magnitude less power than conventional systems. Thanks to their high configurability, they can be used as co-processors in heterogeneous multi-core architectures, and/or directly be placed in critical data paths to reduce the load that hits the system CPU. More...

 


MULTICORES 

During the last few years, there have been radical changes in the hardware and the processor architecture landscape. Intel’s co-founder Gordon E. Moore’s famous conjecture that the number of transistors on integrated circuits doubles roughly every two years still holds today. However, multi-core processors caused a paradigm shift in hardware where increasing number of transistors are invested in parallelism and advanced features on chip designs. In addition to increasing core counts, sophisticated features like advanced instruction sets, SIMD instructions, simultaneous multi-threading (SMT), larger and multiple layers of caches are being introduced in the newer processor designs. All of these game-changing technological trends constitute the driving force behind how new data processing systems and algorithms should be designed and tailored today, albeit making it even more challenging. Moreover, as there are no established designs for the contemporary multicores, there is also no clear consensus on how to design data processing algorithms to take advantage of available features as well as suggest new features to the hardware architects. In this research area, we design novel hardware-conscious algorithms and systems that are targeted to the recent features in hardware to extract the performance premises of modern multi-core machines and which provide insights for upcoming generations of multicores. More... 

 


Rack-scale data processing system

We are building a data appliance for Rack-scale Computers (RaSC) that leverages the benefits of cross-layer optimization and provides support for heterogeneous workloads. To achieve that we separate the storage from the data processing layer. The two layers communicate over a scalable interconnect fabric, at the moment focusing on RDMA over InfiniBand. More...

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