Research

Spring 2016


Time and Location

The lunch seminar is held every Friday from 12:15 to 13:15h at CAB E 72 (lunch provided at 12:00).

Lunch Seminar organizers:

Stefan Kaestle, Anja Gruenheid, David Sidler, Sabela Ramos

 

The topic will be announced shortly before the talk.

Date Speaker Institute Topic Food
 26.02.2016

Reto Achermann,

Stefan Kaestle

 SG

Smelt: Machine-aware Atomic Broadcast Trees for Multicores

 Haecki, Roni (Bagels)
 04.03.2016 Ingo Müller  SG

Engineering Aggregation Operators for Relational In-Memory Database Systems (PhD Thesis)

 Gysi, Tobias (Pizza)
 11.03.2016 Onur Kocberber  Oracle Labs  Accelerators for Data Processing (PhD Thesis)  Kara, Kaan (Libanese Sandwiches)
 18.03.2016  John Liagouris  SG Explaining Outputs in Modern Data Analytics Nushi, Besmira (Hot Pasta)
 25.03.2016 Good Friday      
 01.04.2016 5 Minute Madness     5 Minute Madness   Marroquin, Renato (Döner)
 08.04.2016 Arthur Grevias  System Security Tampering with the Delivery of Blocks and Transactions in Bitcoin Achermann, Reto (Nordsee)
 15.04.2016

Zaheer Chothia

 SG Realising real-time session reconstruction   Humbel, Lukas (Pizza)
 22.04.2016

Maciej Besta

 SG Accelerating Irregular Computations with HardwareTransactional Memory and Active Messages  Di Girolamo, Salvatore (Bagels)
 29.04.2016 Desislava Dimitrova  SG Program me a network  Schneider, Timo (Pasta)
 06.05.2016 David Cock  SG Litmus Testing at Rack Scale  Liagouris, John (Turkish Pizza)
 13.05.2016

Grzegorz Kwasniewski

 SG A PCIe Congestion-Aware Performance Model for Densely Populated Accelerator Servers

Makreshanski, Darko (Döner)

 20.05.2016 Muhsen Owaida  SG Database Acceleration on CPU-FPGA Shared Memory Platforms Grosser, Tobias (Bagels)
 27.05.2016 Philipp Miedl  TIK On the Capacity of Thermal Covert Channels in Multicores Besta, Maciej
 03.06.2016 Timo Schneider  SG   Owaida, Muhsen

 

Fall 2015


Time and Location

The lunch seminar is held every Friday from 12:15 to 13:15h at CAB E 72 (lunch provided at 12:00).

 

Lunch Seminar organizers:

Jonas Pfefferle, Moritz Hoffmann, Besmira Nushi, Tobias Grosser

 

The topic will be announced shortly before the talk.

Date Speaker Institute Topic Food

18.09.2015

Frank McSherry

SG

Differential Dataflow

Kaestle, Stefan (Pizza)

25.09.2015

Raychev Veselin

SPCL

Parallelizing User-Defined Aggregations using Symbolic Execution

Zellweger, Gerd

02.10.2015

Lucas Braun

SG

MTSQL - A Relational Algebra for Multi-Tenancy

Barthels, Claude (Bagels)

09.10.2015

Arijit Khan

SG

Querying Big-graphs - Streaming and Beyond

Marroquin, Renato  (Doner)

16.10.2015

5 Minute Madness

SG

Zsolt Istvan, Edgar Solomonik, David Sidler, Zaheer Chothia, Sabela Ramos, Grzegorz Kwasniewski

Sidler, David (PizzaLemon)

23.10.2015

Tobias Gysi

SPCL

STELLA: A Domain-specific Tool for Structured Grid Methods in Weather and Climate Models

Chothia, Zaheer (Hot Pasta)

30.10.2015

 

 

 

István, Zsolt (NordSee)

06.11.2015

Akhi Singhania

 

Unleashing the performance of 10G NICs

Mueller, Stefan (Bagels)

13.11.2015

Simon Gerber

SG

Cichlid: Explicit physical memory management for large machines

Shinde, Pravin (LebaneseWrap)

20.11.2015

Gerd Zellweger

SG

SpaceJMP: Programming with Multiple Virtual Address Spaces

Roy, Pratanu (PizzaDieci)

27.11.2015

Besmira Nushi

SG

Crowdsourcing Component-based Error Diagnosis of Intelligent Systems

Makreshanski, Darko (HotPasta)

04.12.2015

Pierre-Evariste Dagand

SG

 Programming with Streams

Giceva, Jana
(Nordsee)

11.12.2015

5 minute madness

 

 Desislava Dimitrova, Markus Pilman, Renato Marroquin, Moritz Hoffman, David Stolz, Timo Schneider

Gerber, Simon (Bagels)

18.12.2015

Jana Giceva

SG

Basslet: OS support for parallel data processing on modern multi-cores

Braun, Lucas

 

Data Processing on Modern Hardware

FPGA

The limitations of today's computing architectures are well known: high power consumption, heat dissipation, network and I/O bottlenecks, and the memory wall. Field-programmable gate arrays (FPGAs), user-configurable hardware chips, are promising candidates to overcome these limitations. With tailor-made and software-configured hardware circuits it is possible to process data at very high throughput rates and with extremely low latency. Yet, FPGAs consume orders of magnitude less power than conventional systems. Thanks to their high configurability, they can be used as co-processors in heterogeneous multi-core architectures, and/or directly be placed in critical data paths to reduce the load that hits the system CPU. More...

 


MULTICORES 

During the last few years, there have been radical changes in the hardware and the processor architecture landscape. Intel’s co-founder Gordon E. Moore’s famous conjecture that the number of transistors on integrated circuits doubles roughly every two years still holds today. However, multi-core processors caused a paradigm shift in hardware where increasing number of transistors are invested in parallelism and advanced features on chip designs. In addition to increasing core counts, sophisticated features like advanced instruction sets, SIMD instructions, simultaneous multi-threading (SMT), larger and multiple layers of caches are being introduced in the newer processor designs. All of these game-changing technological trends constitute the driving force behind how new data processing systems and algorithms should be designed and tailored today, albeit making it even more challenging. Moreover, as there are no established designs for the contemporary multicores, there is also no clear consensus on how to design data processing algorithms to take advantage of available features as well as suggest new features to the hardware architects. In this research area, we design novel hardware-conscious algorithms and systems that are targeted to the recent features in hardware to extract the performance premises of modern multi-core machines and which provide insights for upcoming generations of multicores. More... 

 


Rack-scale data processing system

We are building a data appliance for Rack-scale Computers (RaSC) that leverages the benefits of cross-layer optimization and provides support for heterogeneous workloads. To achieve that we separate the storage from the data processing layer. The two layers communicate over a scalable interconnect fabric, at the moment focusing on RDMA over InfiniBand. More...

Back to Research